Mechanical Dimensions & Land Pattern (SSOP-24)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
8.20 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=1.85mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.60 mm
Pins / Total PadsTopology
24P / 24Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SSOP-24 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — MCP3909-I/SS (SSOP-24)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of MCP3909-I/SS (SSOP-24)?
Manufactured by MICROCHIP, the MCP3909-I/SS is housed in a SSOP-24 package with 24 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 4.5V to 5.5V. Key pins include: 1 (DV DD: Multiplexed I/O & Peripheral Pin DV DD (General)), 2 (HPF: Multiplexed I/O & Peripheral Pin HPF (General)), 3 (AV DD: Multiplexed I/O & Peripheral Pin AV DD (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (CH0+: Multiplexed I/O & Peripheral Pin CH0+ (General)), 6 (CH0 -: Multiplexed I/O & Peripheral Pin CH0 - (General)).
What are the IPC-7351B PCB Footprint dimensions for MCP3909-I/SS?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP3909-I/SS (SSOP-24) has a nominal body envelope of 5.30 × 8.20 mm, pitch e = 0.65 mm, and 24 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP3909-I/SS?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP3909-I/SS (MICROCHIP, SSOP-24) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (24 pins) & MCP3909 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | DV DD | Digital_IO | Signal terminal DV DD (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: DV DD. Supported peripheral buses: General. |
| 2 | HPF | Digital_IO | Signal terminal HPF (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: HPF. Supported peripheral buses: General. |
| 3 | AV DD | Digital_IO | Signal terminal AV DD (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: AV DD. Supported peripheral buses: General. |
| 4 | NC | NC | Signal terminal NC (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 5 | CH0+ | Digital_IO | Signal terminal CH0+ (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: CH0+. Supported peripheral buses: General. |
| 6 | CH0 - | Digital_IO | Signal terminal CH0 - (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: CH0 -. Supported peripheral buses: General. |
| 7 | CH1 - | Digital_IO | Signal terminal CH1 - (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: CH1 -. Supported peripheral buses: General. |
| 8 | CH1+ | Digital_IO | Signal terminal CH1+ (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: CH1+. Supported peripheral buses: General. |
| 9 | MCLR | Digital_IO | Signal terminal MCLR (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: MCLR. Supported peripheral buses: General. |
| 10 | REFIN/OUT | Digital_IO | Signal terminal REFIN/OUT (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: REFIN/OUT. Supported peripheral buses: General. |
| 11 | A GND | GND | 0V electrical ground return terminal (A GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 12 | SCK/F2 | Digital_IO | Signal terminal SCK/F2 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: SCK/F2. Supported peripheral buses: SPI. |
| 13 | SDI/F1 | Digital_IO | Signal terminal SDI/F1 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: SDI/F1. Supported peripheral buses: General. |
| 14 | CS/F0 | Digital_IO | Signal terminal CS/F0 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: CS/F0. Supported peripheral buses: General. |
| 15 | G1 | Digital_IO | Signal terminal G1 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: G1. Supported peripheral buses: General. |
| 16 | G0 | Digital_IO | Signal terminal G0 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: G0. Supported peripheral buses: General. |
| 17 | OSC1 | Digital_IO | Signal terminal OSC1 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: OSC1. Supported peripheral buses: RTC/CLK. |
| 18 | OSC2 | Digital_IO | Signal terminal OSC2 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: OSC2. Supported peripheral buses: RTC/CLK. |
| 19 | NC | NC | Signal terminal NC (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 20 | SDO/NEG | Digital_IO | Signal terminal SDO/NEG (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: SDO/NEG. Supported peripheral buses: General. |
| 21 | D GND | GND | 0V electrical ground return terminal (D GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 22 | HF OUT | Digital_IO | Signal terminal HF OUT (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: HF OUT. Supported peripheral buses: General. |
| 23 | F OUT1 | Digital_IO | Signal terminal F OUT1 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: F OUT1. Supported peripheral buses: General. |
| 24 | F OUT0 | Digital_IO | Signal terminal F OUT0 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: F OUT0. Supported peripheral buses: General. |