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GD32F425VGH6 (BGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

GD32F425VGH6

GigaDevice Semicon BeijingID: C5110339BGA-100 · 100 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · GD32F425VGH6 (BGA-100)A1PE3A2PE1A3PB8A4BOOT0A5PD7A6PD5A7PB4A8PB3A9PA15A10PA14A11PA13A12PA12B1PE4B2PE2B3PB9B4PB7B5PB6B6PD6B7PD4B8PD3B9PD1B10PC12B11PC10B12PA11C1PC13 - TAMPEC2PE5C3PE0C4VDDC5PB5C8PD2C9PD0C10PC11C11NCC12PA10D1PC14 - OSC32D2PE6D3VSSD10PA9D11PA8D12PC9E1PC15 - OSC32E2VBATE3NCE10PC8E11PC7E12PC6F1PH0F2VSSF11VSSF12VSSM12PE15M11PE14M10PE13M9PE11M8PE9M7PE7M6PB1M5PB0M4PA7M3PA4M2PA1M1VDDAL12PB12L11NCL10PB10L9PE12L8PE10L7PE8L6PB2L5PC5L4PA6L3PA3L2PA0 - WKUPL1VREFPK12PB13K11PB14K10PB15K9PB11K8PD9K5PC4K4PA5K3PA2K2PC3K1VREFNJ12PD10J11PD11J10PD12J3PC2J2PC1J1VSSAH12PD13H11PD14H10PD15H3PDR_ONH2NRSTH1PC0G12VDDG11VDDG2VDDG1PH1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1L1M1A2B2C2D2E2F2G2H2J2K2L2M2A3B3C3D3E3H3J3K3L3M3A4B4C4K4L4M4A5B5C5K5L5M5A6B6L6M6A7B7L7M7A8B8C8K8L8M8A9B9C9K9L9M9A10B10C10D10E10H10J10K10L10M10A11B11C11D11E11F11G11H11J11K11L11M11A12B12C12D12E12F12G12H12J12K12L12M12E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
A2PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
A3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C, CAN)
A4BOOT0IInput-Only Pin BOOT0 (General)
A5PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
A6PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
A7PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, I2C, SWD/JTAG)
A8PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
A9PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, SWD/JTAG)
A10PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
A11PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
A12PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
B1PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
B2PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
B3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, I2C, CAN)
B4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
B6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
B7PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
B8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
B9PD1I/OMultiplexed I/O & Peripheral Pin PD1 (SPI, CAN)
B10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI, I2C)
B11PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
B12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, CAN)
C1PC13 - TAMPER - RTCI/OMultiplexed I/O & Peripheral Pin PC13 - TAMPER - RTC (RTC/CLK)
C2PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
C3PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
C4VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
C5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (USB, SPI, I2C, CAN)
C8PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
C9PD0I/OMultiplexed I/O & Peripheral Pin PD0 (SPI, CAN)
C10PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
C11NCI/OMultiplexed I/O & Peripheral Pin NC (General)
C12PA10I/OMultiplexed I/O & Peripheral Pin PA10 (USB, UART, I2C)
D1PC14 - OSC32INI/OMultiplexed I/O & Peripheral Pin PC14 - OSC32IN (RTC/CLK)
D2PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
D3VSSGNDGround Reference Pin (VSS)
D10PA9I/OMultiplexed I/O & Peripheral Pin PA9 (USB, UART, SPI, I2C)
D11PA8I/OMultiplexed I/O & Peripheral Pin PA8 (USB, I2C)
D12PC9I/OMultiplexed I/O & Peripheral Pin PC9 (I2C)
E1PC15 - OSC32OU TI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32OU T (RTC/CLK)
E2VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
E3NCI/OMultiplexed I/O & Peripheral Pin NC (General)
E10PC8I/OMultiplexed I/O & Peripheral Pin PC8 (UART)
E11PC7I/OMultiplexed I/O & Peripheral Pin PC7 (UART, SPI)
E12PC6I/OMultiplexed I/O & Peripheral Pin PC6 (UART)
F1PH0I/OMultiplexed I/O & Peripheral Pin PH0 (RTC/CLK)
F2VSSGNDGround Reference Pin (VSS)
F11VSSGNDGround Reference Pin (VSS)
F12VSSGNDGround Reference Pin (VSS)
G1PH1I/OMultiplexed I/O & Peripheral Pin PH1 (RTC/CLK)
G2VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
G11VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
G12VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
H1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (USB, ADC)
H2NRSTISystem Enable & Hardware Reset (NRST)
H3PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
H10PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
H11PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
H12PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
J1VSSAGNDGround Reference Pin (VSSA)
J2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, ADC)
J3PC2I/OMultiplexed I/O & Peripheral Pin PC2 (USB, SPI, ADC)
J10PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART)
J11PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART)
J12PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART)
K1VREFNAnalogMultiplexed I/O & Peripheral Pin VREFN (General)
K2PC3I/OMultiplexed I/O & Peripheral Pin PC3 (USB, SPI, ADC)
K3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
K4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (USB, SPI, ADC)
K5PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
K8PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
K9PB11I/OMultiplexed I/O & Peripheral Pin PB11 (USB, I2C)
K10PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, RTC/CLK)
K11PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART)
K12PB13I/OMultiplexed I/O & Peripheral Pin PB13 (USB, UART, SPI, I2C, CAN)
L1VREFPAnalogMultiplexed I/O & Peripheral Pin VREFP (General)
L2PA0 - WKUPI/OMultiplexed I/O & Peripheral Pin PA0 - WKUP (UART, ADC)
L3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (USB, UART, ADC)
L4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
L5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART)
L6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (USB, SPI)
L7PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
L8PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
L9PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
L10PB10I/OMultiplexed I/O & Peripheral Pin PB10 (USB, UART, SPI, I2C)
L11NCI/OMultiplexed I/O & Peripheral Pin NC (General)
L12PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
M1VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
M2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
M3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (USB, SPI, ADC)
M4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
M5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (USB, SPI, ADC)
M6PB1I/OMultiplexed I/O & Peripheral Pin PB1 (USB, ADC)
M7PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
M8PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
M9PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
M10PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
M11PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
M12PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
PIN A1 PE3
I/O
Multiplexed I/O & Peripheral Pin PE3 (General)
Design note: Default:PE3
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: GD32F425VGH6 (GigaDevice Semicon Beijing · BGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
GD32F425VGH6 (BGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
GD32F425VGH6 (BGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
GD32F425VGH6 (BGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
GD32F425VGH6 (BGA-100) - 4. Package Dimensions (D×E×A)
BGA-100 · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
GD32F425VGH6 (BGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
GD32F425VGH6 (BGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for GD32F425
P11 · p11_fig01EXACT PACKAGE
GD32F425VGH6 (BGA-100) — Figure 2-2. GD32F425Vx BGA100 pinouts
Figure 2-2. GD32F425Vx BGA100 pinouts
P13 · p13_fig01EXACT PACKAGE
GD32F425VGH6 (BGA-100) — Figure 2-5. GD32F425Rx LQFP64 pinouts
Figure 2-5. GD32F425Rx LQFP64 pinouts
P95 · p95_fig01EXACT PACKAGE
GD32F425VGH6 (BGA-100) — Figure 5-3. BGA100 package outline
Figure 5-3. BGA100 package outline
P96 · p96_fig01EXACT PACKAGE
GD32F425VGH6 (BGA-100) — Figure 5-4. BGA100 recommended footprint
Figure 5-4. BGA100 recommended footprint
P62 · p62_fig011261×1034px
GD32F425VGH6 (BGA-100) — Figure 4-1. Recommended power supply decoupling capacitors(1) (2)
Figure 4-1. Recommended power supply decoupling capacitors(1) (2)
P62 · p62_fig021474×980px
GD32F425VGH6 (BGA-100) — Table 4-3. Clock frequency(1) | Symbol Parameter Conditions Min Max Unit | fHCLK AHB clock frequency - - 200 MHz | fAPB1 APB1 clock frequency - - 50 MHz | fAPB2 APB2 clock frequency - - 100 MHz | (1) Guaranteed by design, not tested in prod
Table 4-3. Clock frequency(1) | Symbol Parameter Conditions Min Max Unit | fHCLK AHB clock frequency - - 200 MHz | fAPB1 APB1 clock frequency - - 50 MHz | fAPB2 APB2 clock frequency - - 100 MHz | (1) Guaranteed by design, not tested in prod
P62 · p62_fig01P62
GD32F425VGH6 (BGA-100) — Datasheet Page 62 (p62_fig01)
Datasheet Page 62 (p62_fig01)
P94 · p94_fig011171×1215px
GD32F425VGH6 (BGA-100) — Figure 5-2. LQFP144 recommended footprint
Figure 5-2. LQFP144 recommended footprint
P96 · p96_fig01P96
GD32F425VGH6 (BGA-100) — Datasheet Page 96 (p96_fig01)
Datasheet Page 96 (p96_fig01)
P98 · p98_fig011166×1227px
GD32F425VGH6 (BGA-100) — Figure 5-6. LQFP100 recommended footprint
Figure 5-6. LQFP100 recommended footprint
P13 · p13_fig02All Packages in PDF
GD32F425VGH6 (BGA-100) — Figure 2-5. GD32F425Rx LQFP64 pinouts
Figure 2-5. GD32F425Rx LQFP64 pinouts

Technical Specifications & Part Details (GD32F425VGH6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:GD32F425VGH6 (BGA-100) is a 100-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.35 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, CAN, RTC/CLK, SWD/JTAG, USB interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
40 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.35 mm (A1=0.30 mm)
Package family: BGA (BGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, CAN, RTC/CLK, SWD/JTAG, USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (BGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.50mm
Pad Size (W × L)Level B
0.22 × 0.22 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
BGA-100
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — GD32F425VGH6 (BGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of GD32F425VGH6 (BGA-100)?

Manufactured by GigaDevice Semicon Beijing, the GD32F425VGH6 is housed in a BGA-100 package with 100 pins and a 0.50 mm lead pitch. Key pins include: A1 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), A2 (PE1: Multiplexed I/O & Peripheral Pin PE1 (General)), A3 (PB8: Multiplexed I/O & Peripheral Pin PB8 (I2C, CAN)), A4 (BOOT0: Input-Only Pin BOOT0 (General)), A5 (PD7: Multiplexed I/O & Peripheral Pin PD7 (General)), A6 (PD5: Multiplexed I/O & Peripheral Pin PD5 (General)).

What are the IPC-7351B PCB Footprint dimensions for GD32F425VGH6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), GD32F425VGH6 (BGA-100) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for GD32F425VGH6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for GD32F425VGH6 (GigaDevice Semicon Beijing, BGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & GD32F425 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PE3Digital_IOSignal terminal PE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
A2PE1Digital_IOSignal terminal PE1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
A3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C0_SCL. Supported peripheral buses: I2C, CAN.
A4BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A5PD7Digital_IOSignal terminal PD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
A6PD5Digital_IOSignal terminal PD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
A7PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI0_MISOSPI2MISO, I2C0_TXFRAME. Supported peripheral buses: SPI, I2C, SWD/JTAG.
A8PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
A9PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI0_NSSSPI2NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
A10PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
A11PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
A12PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART, CAN.
B1PE4Digital_IOSignal terminal PE4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
B2PE2Digital_IOSignal terminal PE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
B3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C0_SDA, SPI1_NSS. Supported peripheral buses: SPI, I2C, CAN.
B4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: I2C.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C0_SCL. Supported peripheral buses: UART, I2C.
B6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
B7PD4Digital_IOSignal terminal PD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
B8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
B9PD1Digital_IOSignal terminal PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, CAN.
B10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SDA, SPI2_MOSI. Supported peripheral buses: UART, SPI, I2C.
B11PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI.
B12PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: USB, UART, CAN.
C1PC13 - TAMPER - RTCDigital_IOSignal terminal PC13 - TAMPER - RTC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13 - TAMPER - RTC. Supported peripheral buses: RTC/CLK.
C2PE5Digital_IOSignal terminal PE5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
C3PE0Digital_IOSignal terminal PE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
C4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
C5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C0_SMBA, SPI0_MOSISPI2MOSI. Supported peripheral buses: USB, SPI, I2C, CAN.
C8PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
C9PD0Digital_IOSignal terminal PD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, CAN.
C10PC11Digital_IOSignal terminal PC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART, SPI.
C11NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
C12PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C2_TXFRAME. Supported peripheral buses: USB, UART, I2C.
D1PC14 - OSC32INDigital_IOSignal terminal PC14 - OSC32IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14 - OSC32IN. Supported peripheral buses: RTC/CLK.
D2PE6Digital_IOSignal terminal PE6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
D3VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D10PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C2_SMBA, SPI1_SCKI2S1CK. Supported peripheral buses: USB, UART, SPI, I2C.
D11PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: USB, I2C.
D12PC9Digital_IOSignal terminal PC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: I2C.
E1PC15 - OSC32OU TDigital_IOSignal terminal PC15 - OSC32OU T (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15 - OSC32OU T. Supported peripheral buses: RTC/CLK.
E2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E3NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
E10PC8Digital_IOSignal terminal PC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC8. Supported peripheral buses: UART.
E11PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_SCKI2S1CK. Supported peripheral buses: UART, SPI.
E12PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: UART.
F1PH0Digital_IOSignal terminal PH0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH0. Supported peripheral buses: RTC/CLK.
F2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F11VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F12VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
G1PH1Digital_IOSignal terminal PH1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH1. Supported peripheral buses: RTC/CLK.
G2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
G11VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
G12VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
H1PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: USB, ADC.
H2NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
H3PDR_ONDigital_IOSignal terminal PDR_ON (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
H10PD15Digital_IOSignal terminal PD15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
H11PD14Digital_IOSignal terminal PD14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
H12PD13Digital_IOSignal terminal PD13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
J1VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
J2PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC.
J3PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: USB, SPI, ADC.
J10PD12Digital_IOSignal terminal PD12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD12. Supported peripheral buses: UART.
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