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Mechanical Dimensions & Land Pattern (QFN-20(3x3))
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-20(3x3) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH585D (QFN-20(3x3))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH585D (QFN-20(3x3))?
Manufactured by WCH, the CH585D is housed in a QFN-20(3x3) package with 21 pins and a 0.40 mm lead pitch. Key pins include: 1 (PA10: Multiplexed I/O & Peripheral Pin PA10 (General)), 2 (VDCID: Multiplexed I/O & Peripheral Pin VDCID (General)), 3 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 4 (VDD33: Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)), 5 (PB15/TCK/MISO_: Multiplexed I/O & Peripheral Pin PB15/TCK/MISO_ (SPI)), 6 (PB9（4） PB8: Multiplexed I/O & Peripheral Pin PB9（4） PB8 (General)).
What are the IPC-7351B PCB Footprint dimensions for CH585D?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH585D (QFN-20(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.40 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.80 × 1.80 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH585D?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH585D (WCH, QFN-20(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (21 pins) & CH584 / CH585 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General. |
| 2 | VDCID | Digital_IO | Signal terminal VDCID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCID. Supported peripheral buses: General. |
| 3 | VSW | Digital_IO | Signal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General. |
| 4 | VDD33 | Power_In | Primary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 5 | PB15/TCK/MISO_ | Digital_IO | Signal terminal PB15/TCK/MISO_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI. |
| 6 | PB9（4） PB8 | Digital_IO | Signal terminal PB9（4） PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9（4） PB8. Supported peripheral buses: General. |
| 7 | PB17 | Digital_IO | Signal terminal PB17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB17. Supported peripheral buses: General. |
| 8 | PB16 | Digital_IO | Signal terminal PB16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB16. Supported peripheral buses: General. |
| 9 | PB15（3）I/O/5VT | Power_In | Primary positive power supply input (PB15（3）I/O/5VT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 10 | PB14（3）I/O/5VT | Power_In | Primary positive power supply input (PB14（3）I/O/5VT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 11 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: UART, SPI, I2C. |
| 12 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: UART, I2C. |
| 13 | PB11 | Digital_IO | Signal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: USB. |
| 14 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General. |
| 15 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART, PWM. |
| 16 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART, PWM. |
| 17 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: UART. |
| 18 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: UART, PWM. |
| 19 | PA13/SCK0/PWM5/A3 | Digital_IO | Signal terminal PA13/SCK0/PWM5/A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI, PWM. |
| 20 | PB22 | Digital_IO | Signal terminal PB22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB22. Supported peripheral buses: UART. |
| 21 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |