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ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP32-H2-MINI-1-H4S

ESPRESSIFID: C47967030SMD,16.6x13.2mm · 53 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm)1GND2GND33V34NC5IO26IO37NC8EN9IO010IO111GND12IO1313IO1414GND15VBAT16IO1217NC18IO419IO520IO1021IO1122IO823IO924IO2225IO2526IO2627IO2753GND52GND51GND50GND49GND48GND47GND46GND45GND44GND43GND42GND41GND40GND39GND38GND37GND36GND35NC34NC33NC32NC31TXD030RXD029NC28NCGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.840.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6mm
2. 2D FOOTPRINT
ANTENNA KEEPOUT (5.4mm)12345678910111213141516171819202122232425262728293031323334353637383940414243444546474850515253494949494949494949E=13.20mm · Pitch e=0.80mmD=16.60mm-11-9-7-5-3-11357911121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 13.20mm × 16.60mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (53/53)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GNDGNDGround Reference Pin (GND)
2GNDGNDGround Reference Pin (GND)
33V3PowerPower Supply Input (3V3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
4NCI/OMultiplexed I/O & Peripheral Pin NC (General)
5IO2I/OMultiplexed I/O & Peripheral Pin IO2 (SPI, ADC, SWD/JTAG)
6IO3I/OMultiplexed I/O & Peripheral Pin IO3 (SPI, ADC, SWD/JTAG)
7NCI/OMultiplexed I/O & Peripheral Pin NC (General)
8ENISystem Enable & Hardware Reset (EN)
9IO0I/OMultiplexed I/O & Peripheral Pin IO0 (SPI)
10IO1I/OMultiplexed I/O & Peripheral Pin IO1 (SPI, ADC)
11GNDGNDGround Reference Pin (GND)
12IO13I/OMultiplexed I/O & Peripheral Pin IO13 (RTC/CLK)
13IO14I/OMultiplexed I/O & Peripheral Pin IO14 (RTC/CLK)
14GNDGNDGround Reference Pin (GND)
15VBATPowerPower Supply Input (VBAT — 3.3V VDD3P3 (3.0V ~ 3.6V))
16IO12I/OMultiplexed I/O & Peripheral Pin IO12 (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18IO4I/OMultiplexed I/O & Peripheral Pin IO4 (SPI, ADC, SWD/JTAG)
19IO5I/OMultiplexed I/O & Peripheral Pin IO5 (SPI, ADC, SWD/JTAG)
20IO10I/OMultiplexed I/O & Peripheral Pin IO10 (General)
21IO11I/OMultiplexed I/O & Peripheral Pin IO11 (General)
22IO8I/OMultiplexed I/O & Peripheral Pin IO8 (General)
23IO9I/OMultiplexed I/O & Peripheral Pin IO9 (General)
24IO22I/OMultiplexed I/O & Peripheral Pin IO22 (General)
25IO25I/OMultiplexed I/O & Peripheral Pin IO25 (SPI)
26IO26I/OMultiplexed I/O & Peripheral Pin IO26 (USB, SPI)
27IO27I/OMultiplexed I/O & Peripheral Pin IO27 (USB, SPI)
28NCI/OMultiplexed I/O & Peripheral Pin NC (General)
29NCI/OMultiplexed I/O & Peripheral Pin NC (General)
30RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART, SPI)
31TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART, SPI)
32NCI/OMultiplexed I/O & Peripheral Pin NC (General)
33NCI/OMultiplexed I/O & Peripheral Pin NC (General)
34NCI/OMultiplexed I/O & Peripheral Pin NC (General)
35NCI/OMultiplexed I/O & Peripheral Pin NC (General)
36GNDGNDGround Reference Pin (GND)
37GNDGNDGround Reference Pin (GND)
38GNDGNDGround Reference Pin (GND)
39GNDGNDExposed Thermal & Ground Pad (GND)
40GNDGNDGround Reference Pin (GND)
41GNDGNDGround Reference Pin (GND)
42GNDGNDGround Reference Pin (GND)
43GNDGNDGround Reference Pin (GND)
44GNDGNDGround Reference Pin (GND)
45GNDGNDGround Reference Pin (GND)
46GNDGNDGround Reference Pin (GND)
47GNDGNDGround Reference Pin (GND)
48GNDGNDGround Reference Pin (GND)
49GNDGNDExposed Thermal & Ground Pad (GND)
50GNDGNDGround Reference Pin (GND)
51GNDGNDGround Reference Pin (GND)
52GNDGNDGround Reference Pin (GND)
53GNDGNDGround Reference Pin (GND)
PIN 1 GND
GND
Ground Reference Pin (GND)
Design note: Ground
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 20 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP32-H2-MINI-1-H4S (ESPRESSIF · SMD,16.6x13.2mm)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) - 2. Standard Pinout (Top View)
True package pinout (53 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) - 4. Package Dimensions (D×E×A)
SMD,16.6x13.2mm · 13.20×16.60mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) - 5. Recommended Land Pattern
IPC-7351B Footprint (61 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (20 figures · Page 1/2)
Showing 1–12 of 20 uncropped original figures for ESP32-H2-MINI
P1 · p01_fig01EXACT PACKAGE
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — ESP32-H2-MINI-1 ESP32-H2-MINI-1U
ESP32-H2-MINI-1 ESP32-H2-MINI-1U
P1 · p01_fig02EXACT PACKAGE
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — ESP32-H2-MINI-1 ESP32-H2-MINI-1U
ESP32-H2-MINI-1 ESP32-H2-MINI-1U
P32 · p32_fig01EXACT PACKAGE
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — Figure 5: ESP32-H2-MINI-1 Schematics
Figure 5: ESP32-H2-MINI-1 Schematics
P32 · p32_fig02EXACT PACKAGE
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — Figure 5: ESP32-H2-MINI-1 Schematics
Figure 5: ESP32-H2-MINI-1 Schematics
P32 · p32_fig03EXACT PACKAGE
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — Figure 5: ESP32-H2-MINI-1 Schematics
Figure 5: ESP32-H2-MINI-1 Schematics
P34 · p34_fig01EXACT PACKAGE
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — Figure 7: Peripheral Schematics
Figure 7: Peripheral Schematics
P35 · p35_fig01EXACT PACKAGE
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — Figure 8: ESP32-H2-MINI-1 Physical Dimensions
Figure 8: ESP32-H2-MINI-1 Physical Dimensions
P35 · p35_fig02EXACT PACKAGE
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — Figure 9: ESP32-H2-MINI-1U Physical Dimensions
Figure 9: ESP32-H2-MINI-1U Physical Dimensions
P38 · p38_fig01EXACT PACKAGE
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — Figure 11: ESP32-H2-MINI-1 Recommended PCB Land Pattern
Figure 11: ESP32-H2-MINI-1 Recommended PCB Land Pattern
P1 · p01_fig03336×313px
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — 5) ESPRESSIF
5) ESPRESSIF
P1 · p01_fig02P1
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P9 · p09_fig011229×1401px
ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) — Figure 3: Pin Layout (Top View)
Figure 3: Pin Layout (Top View)
Page 1 / 2 (20 extracted figures)

Technical Specifications & Part Details (ESP32-H2-MINI-1-H4S)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) is a 53-pin wireless wi-fi / bluetooth le soc module featuring a 16.60 × 13.20 × 2.40 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
96 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_TX(peak) ≈ 310 mA @ 3.3V | Deep-Sleep ≈ 10 µA | I_GPIO(max) = 40 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
16.60 × 13.20 × 2.40 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (SMD,16.6x13.2mm)
Pin Count & Lead PitchN / e
53 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (IO0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol53 auto-grouped pins
OK
IPC-7351B Land Pattern61 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteEPAD 5.45×5.35mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SMD,16.6x13.2mm)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
16.60 × 13.20 mm
Height (A) & Pitch (e)IPC-7351B
A=2.40mm · e=0.80mm
Pad Size (W × L)Level B
0.40 × 0.80 mm
Pins / Total PadsTopology
53P / 61Pad (CASTELLATED_MODULE)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2
BOM
22µF (or 10µF) X5R + 100nF X7R
0805 + 0402
3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA.
R_en + C_en
BOM
R = 10kΩ to 3V3 + C = 1µF to GND
0402 / 0603
Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot.
R_boot + SW1
BOM
10kΩ Pull-up + BOOT button
0402 + SMD
Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download.
D_esd
BOM
USBLC6-2SC6 / LESD5D5.0CT1G
SOT-23-6 / SOD-523
ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20.
ESP32-S3-MINI-1-N8 / 1U-N4R2
Espressif
100% Drop-inSame 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping.

Technical Frequently Asked Questions (FAQ) — ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm)?

Manufactured by ESPRESSIF, the ESP32-H2-MINI-1-H4S is housed in a SMD,16.6x13.2mm package with 53 pins and a 0.80 mm lead pitch. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (GND: Ground Reference Pin (GND)), 3 (3V3: Power Supply Input (3V3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (IO2: Multiplexed I/O & Peripheral Pin IO2 (SPI, ADC, SWD/JTAG)), 6 (IO3: Multiplexed I/O & Peripheral Pin IO3 (SPI, ADC, SWD/JTAG)).

What are the IPC-7351B PCB Footprint dimensions for ESP32-H2-MINI-1-H4S?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-H2-MINI-1-H4S (SMD,16.6x13.2mm) has a nominal body envelope of 13.20 × 16.60 mm, pitch e = 0.80 mm, and 61 copper pads plus a central exposed thermal pad (EPAD) of 5.45 × 5.35 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-H2-MINI-1-H4S?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-H2-MINI-1-H4S (ESPRESSIF, SMD,16.6x13.2mm) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (53 pins) & ESP32-H2-MINI Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
33V3Power_InPrimary positive power supply input (3V3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
4NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
5IO2Digital_IOSignal terminal IO2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO2, FSPIWP, ADC1_CH1, MTMS. Supported peripheral buses: SPI, ADC, SWD/JTAG.
6IO3Digital_IOSignal terminal IO3 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO3, FSPIHD, ADC1_CH2, MTDO. Supported peripheral buses: SPI, ADC, SWD/JTAG.
7NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
8ENDigital_IOChip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
9IO0Digital_IOSignal terminal IO0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO0, FSPIQ. Supported peripheral buses: SPI.
10IO1Digital_IOSignal terminal IO1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO1, FSPICS0, ADC1_CH0. Supported peripheral buses: SPI, ADC.
11GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
12IO13Digital_IOSignal terminal IO13 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO13. Supported peripheral buses: RTC/CLK.
13IO14Digital_IOSignal terminal IO14 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO14. Supported peripheral buses: RTC/CLK.
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
16IO12Digital_IOSignal terminal IO12 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO12. Supported peripheral buses: General.
17NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18IO4Digital_IOSignal terminal IO4 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO4, FSPICLK, ADC1_CH3, MTCK. Supported peripheral buses: SPI, ADC, SWD/JTAG.
19IO5Digital_IOSignal terminal IO5 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO5, FSPID, ADC1_CH4, MTDI. Supported peripheral buses: SPI, ADC, SWD/JTAG.
20IO10Digital_IOSignal terminal IO10 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO10. Supported peripheral buses: General.
21IO11Digital_IOSignal terminal IO11 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO11. Supported peripheral buses: General.
22IO8Digital_IOSignal terminal IO8 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General.
23IO9Digital_IOSignal terminal IO9 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General.
24IO22Digital_IOSignal terminal IO22 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO22. Supported peripheral buses: General.
25IO25Digital_IOSignal terminal IO25 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO25, FSPICS3. Supported peripheral buses: SPI.
26IO26Digital_IOSignal terminal IO26 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO26, FSPICS4. Supported peripheral buses: USB, SPI.
27IO27Digital_IOSignal terminal IO27 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO27, FSPICS5. Supported peripheral buses: USB, SPI.
28NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
29NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
30RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO23, FSPICS1, U0RXD. Supported peripheral buses: UART, SPI.
31TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO24, FSPICS2, U0TXD. Supported peripheral buses: UART, SPI.
32NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
33NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
34NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
35NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
36GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
37GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
38GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
39GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
40GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
41GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
42GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
43GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
44GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
45GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
46GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
47GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
48GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
49GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
50GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
51GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
52GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
53GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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