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STM32F103CBT6-TD (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F103CBT6-TD

TDSEMICID: C46614420LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F103CBT6-TD (LQFP-48(7x7))1VBAT2PC133PC14-OSC32_I4PC15-OSC32_O5PD0-OSC_IN6PD1-OSC_OUT7NRST8VSSA9VDDA10PA0-WKUP11PA112PA213PA314PA415PA516PA617PA718PB019PB120PB2/BOOT121PB1022PB1123VSS_124VDD_148VDD_347VSS_346PB945PB844BOOT043PB742PB641PB540PB439PB338PA1537PA1436VDD_235VSS_234PA1333PA1232PA1131PA1030PA929PA828PB1527PB1426PB1325PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.835.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
3PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
4PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
5PD0-OSC_INI/OMultiplexed I/O & Peripheral Pin PD0-OSC_IN (RTC/CLK)
6PD1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PD1-OSC_OUT (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8VSSAGNDGround Reference Pin (VSSA)
9VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
10PA0-WKUPI/OMultiplexed I/O & Peripheral Pin PA0-WKUP (UART, ADC, PWM)
11PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
12PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
13PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
14PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
15PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
16PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
17PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
18PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
19PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
20PB2/BOOT1I/OMultiplexed I/O & Peripheral Pin PB2/BOOT1 (General)
21PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C, PWM)
22PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C, PWM)
23VSS_1GNDGround Reference Pin (VSS_1)
24VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
25PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
26PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
27PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
28PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM)
29PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
30PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, PWM)
31PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, PWM)
32PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, PWM, CAN)
33PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
34PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
35VSS_2GNDGround Reference Pin (VSS_2)
36VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
37PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
38PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SPI, PWM, SWD/JTAG)
39PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, PWM, SWD/JTAG)
40PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, PWM, SWD/JTAG)
41PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C, PWM)
42PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C, PWM)
43PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C, PWM)
44BOOT0IInput-Only Pin BOOT0 (General)
45PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C, PWM, CAN)
46PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C, PWM, CAN)
47VSS_3GNDGround Reference Pin (VSS_3)
48VDD_3PowerPower Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
Design note: Backup power supply for RTC and backup registers (1.8V ~ 3.6V)
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F103CBT6-TD (TDSEMIC · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F103CBT6-TD (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F103CBT6-TD (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F103CBT6-TD (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F103CBT6-TD (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F103CBT6-TD (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F103CBT6-TD (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for STM32F103
P64 · p64_fig01EXACT PACKAGE
STM32F103CBT6-TD (LQFP-48(7x7)) — a STM32F103CBT6-TD —$~> fA 24 LQFP48, 7x 7mm #4% Layout Mix 0.50 1.20 D000 The 7 ial +——} = — = — = 02 C4 9.70 5.80. id) — — — — = =| 7.30| — — 48 13 ioooooo000t an 5.80 9.70 7.1 HR LR FA 26 HAR LA 9000000000000 | i Dp) [eo] {[o) [a 6 +—© -
a STM32F103CBT6-TD —$~> fA 24 LQFP48, 7x 7mm #4% Layout Mix 0.50 1.20 D000 The 7 ial +——} = — = — = 02 C4 9.70 5.80. id) — — — — = =| 7.30| — — 48 13 ioooooo000t an 5.80 9.70 7.1 HR LR FA 26 HAR LA 9000000000000 | i Dp) [eo] {[o) [a 6 +—© -
P1 · p01_fig012150×3041px
STM32F103CBT6-TD (LQFP-48(7x7)) — PDF Figure p01_fig01 (Page 1 — REPRESENTATIVE_PHOTO)
PDF Figure p01_fig01 (Page 1 — REPRESENTATIVE_PHOTO)
P1 · p01_fig01P1
STM32F103CBT6-TD (LQFP-48(7x7)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig012150×2938px
STM32F103CBT6-TD (LQFP-48(7x7)) — ————————————————————————————— STM32F103CBT6-TD ——_—— JE Armo Cortexo-M3 AKA 32 (xpd fill 2S 1 PRE - fe pay H op re) + rave eneaunnra = 32 fi Arm® Cortex®-M3 Pe - RCO MiernoleN NASI ~ iit SOMA Tes m fash - 2% 12C #0 (1Mbits), 2A Alia SMBus/P
————————————————————————————— STM32F103CBT6-TD ——_—— JE Armo Cortexo-M3 AKA 32 (xpd fill 2S 1 PRE - fe pay H op re) + rave eneaunnra = 32 fi Arm® Cortex®-M3 Pe - RCO MiernoleN NASI ~ iit SOMA Tes m fash - 2% 12C #0 (1Mbits), 2A Alia SMBus/P
P2 · p02_fig01P2
STM32F103CBT6-TD (LQFP-48(7x7)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P63 · p63_fig012150×2938px
STM32F103CBT6-TD (LQFP-48(7x7)) — PDF Figure p63_fig01 (Page 63 — OTHER_DIAGRAM)
PDF Figure p63_fig01 (Page 63 — OTHER_DIAGRAM)
P65 · p65_fig012150×2938px
STM32F103CBT6-TD (LQFP-48(7x7)) — ————————————————————————————— STM32F103CBT6-TD ——_—— 9 MARRS Hie 56 MN INEBUR A ee WWW.TDSEMIC.COM Page 64 BES
————————————————————————————— STM32F103CBT6-TD ——_—— 9 MARRS Hie 56 MN INEBUR A ee WWW.TDSEMIC.COM Page 64 BES
P61 · p61_fig01All Packages in PDF
STM32F103CBT6-TD (LQFP-48(7x7)) — $§$=—=—=S=S=___a—{ STM32F103CBT6-TD ——— 6.2 LQFP64 #3) FA 20 LQFP64 #541 {uuu 4 i ff t { ; tl - +s ' m4 { - | ! 1 7 i (1) PAS REAR Ee Bale fhil (2) ARATNY S| ANA MLIAHE Bete PCB I WWW.TDSEMIC.COM Page 60 RES
$§$=—=—=S=S=___a—{ STM32F103CBT6-TD ——— 6.2 LQFP64 #3) FA 20 LQFP64 #541 {uuu 4 i ff t { ; tl - +s ' m4 { - | ! 1 7 i (1) PAS REAR Ee Bale fhil (2) ARATNY S| ANA MLIAHE Bete PCB I WWW.TDSEMIC.COM Page 60 RES

Technical Specifications & Part Details (STM32F103CBT6-TD)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F103CBT6-TD (LQFP-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated ADC, CAN, I2C, PWM, RTC/CLK, SPI, SWD/JTAG, UART, USB interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
ARM Cortex-M3 72 MHz (HSE 8 MHz / LSE 32.768 kHz)
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
21 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
ADC, CAN, I2C, PWM, RTC/CLK, SPI, SWD/JTAG, UART, USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2/BOOT1, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2, C3
BOM
3× 100nF (0.1µF) 50V X7R
0402 / 0603
Digital supply decoupling caps for VDD_1..3 (Pins 24, 36, 48) — place < 1.5mm from each VDD pin.
C4
BOM
4.7µF ~ 10µF 10V X5R
0603 / 0805
Bulk decoupling capacitor for main VDD rail — place near 3.3V power entry to the MCU.
C5, C6 + FB1
BOM
100nF + 1µF + Ferrite 600Ω@100MHz
0402 / 0603
Analog rail filter for VDDA/VSSA (Pins 8, 9) 12-bit ADC — isolate digital switching noise.
Y1 + C7, C8
BOM
8MHz Crystal (CL=12pF) + 2× 18pF NP0
SMD-3225 + 0402
Main HSE oscillator crystal (Pin 5 PD0, Pin 6 PD1) — route matched traces < 4mm with GND guard ring.
STM32F103CBT6
STMicroelectronics
100% Drop-in100% Drop-in (128KB Flash Upgrade) — identical LQFP-48 pinout with doubled Flash capacity.
GD32F103C8T6
GigaDevice
Pin-to-Pin LQFP-48 (108MHz)Pin-to-Pin LQFP-48 (108MHz) — higher core clock; verify Flash wait-states & USB timing.
APM32F103C8T6
Geehy
Pin-to-Pin LQFP-48 (96MHz)Pin-to-Pin LQFP-48 (96MHz) — direct hardware replacement, register-compatible with STM32F1.

Technical Frequently Asked Questions (FAQ) — STM32F103CBT6-TD (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F103CBT6-TD (LQFP-48(7x7))?

Manufactured by TDSEMIC, the STM32F103CBT6-TD is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14-OSC32_IN: Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)), 4 (PC15-OSC32_OUT: Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)), 5 (PD0-OSC_IN: Multiplexed I/O & Peripheral Pin PD0-OSC_IN (RTC/CLK)), 6 (PD1-OSC_OUT: Multiplexed I/O & Peripheral Pin PD1-OSC_OUT (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32F103CBT6-TD?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103CBT6-TD (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103CBT6-TD?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103CBT6-TD (TDSEMIC, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & STM32F103 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: TAMPER-RTC, RTC_OUT, RTC_CALIB. Supported peripheral buses: RTC/CLK.
3PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC32_IN, PC14. Supported peripheral buses: RTC/CLK.
4PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC32_OUT, PC15. Supported peripheral buses: RTC/CLK.
5PD0-OSC_INDigital_IOSignal terminal PD0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN, PD0. Supported peripheral buses: RTC/CLK.
6PD1-OSC_OUTDigital_IOSignal terminal PD1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT, PD1. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
9VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
10PA0-WKUPAnalogSignal terminal PA0-WKUP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: WKUP, USART2_CTS, ADC12_IN0, TIM2_CH1_ETR. Supported peripheral buses: UART, ADC, PWM.
11PA1AnalogSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USART2_RTS, ADC12_IN1, TIM2_CH2. Supported peripheral buses: UART, ADC, PWM.
12PA2AnalogSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USART2_TX, ADC12_IN2, TIM2_CH3. Supported peripheral buses: UART, ADC, PWM.
13PA3AnalogSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USART2_RX, ADC12_IN3, TIM2_CH4. Supported peripheral buses: UART, ADC, PWM.
14PA4AnalogSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, USART2_CK, ADC12_IN4. Supported peripheral buses: UART, SPI, ADC.
15PA5AnalogSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK, ADC12_IN5. Supported peripheral buses: SPI, ADC.
16PA6AnalogSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO, ADC12_IN6, TIM3_CH1, TIM1_BKIN. Supported peripheral buses: SPI, ADC, PWM.
17PA7AnalogSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI, ADC12_IN7, TIM3_CH2, TIM1_CH1N. Supported peripheral buses: SPI, ADC, PWM.
18PB0AnalogSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: ADC12_IN8, TIM3_CH3, TIM1_CH2N. Supported peripheral buses: ADC, PWM.
19PB1AnalogSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: ADC12_IN9, TIM3_CH4, TIM1_CH3N. Supported peripheral buses: ADC, PWM.
20PB2/BOOT1Digital_IOSignal terminal PB2/BOOT1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: BOOT1, PB2. Supported peripheral buses: General.
21PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL, USART3_TX, TIM2_CH3. Supported peripheral buses: UART, I2C, PWM.
22PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA, USART3_RX, TIM2_CH4. Supported peripheral buses: UART, I2C, PWM.
23VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
24VDD_1Power_InPrimary positive power supply input (VDD_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
25PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA, USART3_CK, TIM1_BKIN. Supported peripheral buses: UART, SPI, I2C.
26PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK, USART3_CTS, TIM1_CH1N. Supported peripheral buses: UART, SPI, PWM.
27PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO, USART3_RTS, TIM1_CH2N. Supported peripheral buses: UART, SPI, PWM.
28PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI, TIM1_CH3N. Supported peripheral buses: SPI, PWM.
29PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USART1_CK, TIM1_CH1, MCO. Supported peripheral buses: UART, PWM, RTC/CLK.
30PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USART1_TX, TIM1_CH2. Supported peripheral buses: UART, PWM.
31PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USART1_RX, TIM1_CH3. Supported peripheral buses: UART, PWM.
32PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USB_DM, CAN_RX, USART1_CTS, TIM1_CH4. Supported peripheral buses: USB, UART, PWM, CAN.
33PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USB_DP, CAN_TX, USART1_RTS, TIM1_ETR. Supported peripheral buses: USB, UART, CAN.
34PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTMS, SWDIO. Supported peripheral buses: SWD/JTAG.
35VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
36VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
37PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTCK, SWCLK. Supported peripheral buses: SWD/JTAG.
38PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTDI, SPI1_NSS, TIM2_CH1_ETR. Supported peripheral buses: SPI, PWM, SWD/JTAG.
39PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTDO, SPI1_SCK, TIM2_CH2, TRACESWO. Supported peripheral buses: SPI, PWM, SWD/JTAG.
40PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: NJTRST, SPI1_MISO, TIM3_CH1. Supported peripheral buses: SPI, PWM, SWD/JTAG.
41PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, TIM3_CH2. Supported peripheral buses: SPI, I2C, PWM.
42PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL, TIM4_CH1, USART1_TX. Supported peripheral buses: UART, I2C, PWM.
43PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, TIM4_CH2, USART1_RX. Supported peripheral buses: UART, I2C, PWM.
44BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
45PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: TIM4_CH3, I2C1_SCL, CAN_RX. Supported peripheral buses: I2C, PWM, CAN.
46PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: TIM4_CH4, I2C1_SDA, CAN_TX. Supported peripheral buses: I2C, PWM, CAN.
47VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
48VDD_3Power_InPrimary positive power supply input (VDD_3) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
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