UDFN-6(2x2) · 7P
Synchronized Pinout (Symbol / 2D / 3D) (7/7)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | OUT | I/O | Multiplexed I/O & Peripheral Pin OUT (General) |
| 2 | ILIM/NC | I/O | Multiplexed I/O & Peripheral Pin ILIM/NC (General) |
| 3 | FLAG# | I/O | Multiplexed I/O & Peripheral Pin FLAG# (General) |
| 4 | EN | I | System Enable & Hardware Reset (EN) |
| 5 | GND | GND | Ground Reference Pin (GND) |
| 6 | IN | I/O | Multiplexed I/O & Peripheral Pin IN (General) |
| 7 | EP | GND | Exposed Thermal & Ground Pad (EP) |
PIN 1 OUT
I/OMultiplexed I/O & Peripheral Pin OUT (General)
Design note: Signal terminal OUT (I/O, 2.5 V – 5.5 V domain). Multiplexed alternate functions: OUT. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (7 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
UDFN-6(2x2) · 2.00×2.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (7 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for NCP380
P1 · p01_fig02EXACT PACKAGE
P2 · p02_fig02EXACT PACKAGE
P21 · p21_fig01EXACT PACKAGE
P1 · p01_fig01424×386px
P2 · p02_fig011522×715px
P2 · p02_fig02P2
P21 · p21_fig01P21
P22 · p22_fig011474×1607px
P23 · p23_fig011402×969px
Technical Specifications & Part Details (NCP380HMU05AATBG)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:NCP380HMU05AATBG (UDFN-6(2x2)) is a 6-pin standard electronic & interconnect component featuring a 2.00 × 2.00 × 0.85 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.5 V – 5.5 V supply operation across 40°C to 125°C with integrated USB interfaces.
Operating Supply VoltageV_CC / V_DD
2.5 V – 5.5 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
40°C to 125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.00 × 2.00 × 0.85 mm (A1=0.03 mm)
Package family: DFN (UDFN-6(2x2))
Pin Count & Lead PitchN / e
6 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol7 auto-grouped pins
IPC-7351B Land Pattern7 pads · Pitch 0.65mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — NCP380 (2)
UDFN-6(2x2) · 7P
Mechanical Dimensions & Land Pattern (UDFN-6(2x2))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
2.00 × 2.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.65mm
Pad Size (W × L)Level B
0.34 × 0.58 mm
Pins / Total PadsTopology
7P / 7Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit UDFN-6(2x2) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — NCP380HMU05AATBG (UDFN-6(2x2))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of NCP380HMU05AATBG (UDFN-6(2x2))?
Manufactured by onsemi, the NCP380HMU05AATBG is housed in a UDFN-6(2x2) package with 7 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.5 V – 5.5 V. Key pins include: 1 (OUT: Multiplexed I/O & Peripheral Pin OUT (General)), 2 (ILIM/NC: Multiplexed I/O & Peripheral Pin ILIM/NC (General)), 3 (FLAG#: Multiplexed I/O & Peripheral Pin FLAG# (General)), 4 (EN: System Enable & Hardware Reset (EN)), 5 (GND: Ground Reference Pin (GND)), 6 (IN: Multiplexed I/O & Peripheral Pin IN (General)).
What are the IPC-7351B PCB Footprint dimensions for NCP380HMU05AATBG?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), NCP380HMU05AATBG (UDFN-6(2x2)) has a nominal body envelope of 2.00 × 2.00 mm, pitch e = 0.65 mm, and 7 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for NCP380HMU05AATBG?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for NCP380HMU05AATBG (onsemi, UDFN-6(2x2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (7 pins) & NCP380 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | OUT | Digital_IO | Signal terminal OUT (I/O, 2.5 V – 5.5 V domain). Multiplexed alternate functions: OUT. Supported peripheral buses: General. |
| 2 | ILIM/NC | Digital_IO | Signal terminal ILIM/NC (I/O, 2.5 V – 5.5 V domain). Multiplexed alternate functions: ILIM/NC. Supported peripheral buses: General. |
| 3 | FLAG# | Digital_IO | Signal terminal FLAG# (I/O, 2.5 V – 5.5 V domain). Multiplexed alternate functions: FLAG#. Supported peripheral buses: General. |
| 4 | EN | Digital_IO | Chip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset. |
| 5 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 6 | IN | Digital_IO | Signal terminal IN (I/O, 2.5 V – 5.5 V domain). Multiplexed alternate functions: IN. Supported peripheral buses: General. |
| 7 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |