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ATF1502AS-7AX44 (TQFP-44(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATF1502AS-7AX44

MICROCHIPID: C461611TQFP-44(10x10) · 44 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATF1502AS-7AX44 (TQFP-44(10x10))1I/O/TDI2I/O3I/O4GND5PD1/I/O6I/O7TMS/I/O8I/O9VCC10I/O11I/O12/O13I/O14I/O15I/O16GND17VCC18I/O19PD2/I/O20I/O21I/O22I/O44I/O43I/O42I/O41VCC40GCLK2/OE2/I39GCLR/I38I/OE137GCLK1/I36GND35GCLK3/I/O34I/O33I/O32I/O/TDO31I/O30I/O29VCC28I/O27I/O26I/O/TCK25I/O24GND23I/OGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.833.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344E=10.00mm · Pitch e=0.80mmD=10.00mm-10-8-6-4-202468101086420-2-4-6-8-10mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (44/44)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1I/O/TDII/OMultiplexed I/O & Peripheral Pin I/O/TDI (General)
2I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
3I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
4GNDGNDGround Reference Pin (GND)
5PD1/I/OI/OMultiplexed I/O & Peripheral Pin PD1/I/O (General)
6I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
7TMS/I/OI/OMultiplexed I/O & Peripheral Pin TMS/I/O (General)
8I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
9VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
10I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
11I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
12/OI/OMultiplexed I/O & Peripheral Pin /O (General)
13I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
14I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
15I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
16GNDGNDGround Reference Pin (GND)
17VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
18I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
19PD2/I/OI/OMultiplexed I/O & Peripheral Pin PD2/I/O (General)
20I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
21I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
22I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
23I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
24GNDGNDGround Reference Pin (GND)
25I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
26I/O/TCKI/OMultiplexed I/O & Peripheral Pin I/O/TCK (General)
27I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
28I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
29VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
30I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
31I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
32I/O/TDOI/OMultiplexed I/O & Peripheral Pin I/O/TDO (General)
33I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
34I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
35GCLK3/I/OI/OMultiplexed I/O & Peripheral Pin GCLK3/I/O (General)
36GNDGNDGround Reference Pin (GND)
37GCLK1/II/OMultiplexed I/O & Peripheral Pin GCLK1/I (General)
38I/OE1I/OMultiplexed I/O & Peripheral Pin I/OE1 (General)
39GCLR/II/OMultiplexed I/O & Peripheral Pin GCLR/I (General)
40GCLK2/OE2/II/OMultiplexed I/O & Peripheral Pin GCLK2/OE2/I (General)
41VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
42I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
43I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
44I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
PIN 1 I/O/TDI
I/O
Multiplexed I/O & Peripheral Pin I/O/TDI (General)
Design note: Signal terminal I/O/TDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O/TDI. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATF1502AS-7AX44 (MICROCHIP · TQFP-44(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATF1502AS-7AX44 (TQFP-44(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATF1502AS-7AX44 (TQFP-44(10x10)) - 2. Standard Pinout (Top View)
True package pinout (44 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATF1502AS-7AX44 (TQFP-44(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATF1502AS-7AX44 (TQFP-44(10x10)) - 4. Package Dimensions (D×E×A)
TQFP-44(10x10) · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATF1502AS-7AX44 (TQFP-44(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (44 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATF1502AS-7AX44 (TQFP-44(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for ATF1502
P26 · p26_fig01EXACT PACKAGE
ATF1502AS-7AX44 (TQFP-44(10x10)) — ATF1502AS(L) [DATASHEET]
ATF1502AS(L) [DATASHEET]
P4 · p04_fig011382×916px
ATF1502AS-7AX44 (TQFP-44(10x10)) — Figure 1-1. Pinouts
Figure 1-1. Pinouts
P4 · p04_fig01P4
ATF1502AS-7AX44 (TQFP-44(10x10)) — Datasheet Page 4 (p04_fig01)
Datasheet Page 4 (p04_fig01)
P26 · p26_fig01P26
ATF1502AS-7AX44 (TQFP-44(10x10)) — Datasheet Page 26 (p26_fig01)
Datasheet Page 26 (p26_fig01)
P27 · p27_fig011963×2267px
ATF1502AS-7AX44 (TQFP-44(10x10)) — 27 ATF1502AS(L) [DATASHEET]
27 ATF1502AS(L) [DATASHEET]

Technical Specifications & Part Details (ATF1502AS-7AX44)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:ATF1502AS-7AX44 (TQFP-44(10x10)) is a 44-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.00 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C to +85°C with integrated JTAG / SWD interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
125MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.00 mm (A1=0.10 mm)
Package family: TQFP (TQFP-44(10x10))
Pin Count & Lead PitchN / e
44 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
JTAG / SWD
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol44 auto-grouped pins
OK
IPC-7351B Land Pattern44 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-44(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.80mm
Pad Size (W × L)Level B
0.50 × 1.50 mm
Pins / Total PadsTopology
44P / 44Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFP-44(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATF1502AS-7AX44 (TQFP-44(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATF1502AS-7AX44 (TQFP-44(10x10))?

Manufactured by MICROCHIP, the ATF1502AS-7AX44 is housed in a TQFP-44(10x10) package with 44 pins and a 0.80 mm lead pitch. Key pins include: 1 (I/O/TDI: Multiplexed I/O & Peripheral Pin I/O/TDI (General)), 2 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), 3 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), 4 (GND: Ground Reference Pin (GND)), 5 (PD1/I/O: Multiplexed I/O & Peripheral Pin PD1/I/O (General)), 6 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)).

What are the IPC-7351B PCB Footprint dimensions for ATF1502AS-7AX44?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATF1502AS-7AX44 (TQFP-44(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 44 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATF1502AS-7AX44?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATF1502AS-7AX44 (MICROCHIP, TQFP-44(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (44 pins) & ATF1502 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1I/O/TDIDigital_IOSignal terminal I/O/TDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O/TDI. Supported peripheral buses: General.
2I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
3I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5PD1/I/ODigital_IOSignal terminal PD1/I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD1/I/O. Supported peripheral buses: General.
6I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
7TMS/I/ODigital_IOSignal terminal TMS/I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TMS/I/O. Supported peripheral buses: General.
8I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
9VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
11I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
12/ODigital_IOSignal terminal /O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: /O. Supported peripheral buses: General.
13I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
14I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
15I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
16GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
17VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
18I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
19PD2/I/ODigital_IOSignal terminal PD2/I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2/I/O. Supported peripheral buses: General.
20I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
21I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
22I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
23I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
24GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
25I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
26I/O/TCKDigital_IOSignal terminal I/O/TCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O/TCK. Supported peripheral buses: General.
27I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
28I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
29VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
30I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
31I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
32I/O/TDODigital_IOSignal terminal I/O/TDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O/TDO. Supported peripheral buses: General.
33I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
34I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
35GCLK3/I/ODigital_IOSignal terminal GCLK3/I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GCLK3/I/O. Supported peripheral buses: General.
36GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
37GCLK1/IDigital_IOSignal terminal GCLK1/I (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GCLK1/I. Supported peripheral buses: General.
38I/OE1Digital_IOSignal terminal I/OE1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/OE1. Supported peripheral buses: General.
39GCLR/IDigital_IOSignal terminal GCLR/I (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GCLR/I. Supported peripheral buses: General.
40GCLK2/OE2/IDigital_IOSignal terminal GCLK2/OE2/I (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GCLK2/OE2/I. Supported peripheral buses: General.
41VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
42I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
43I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
44I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
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