Mechanical Dimensions & Land Pattern (SC-70-5)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SC-70-5 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — MIC5365-1.2YC5-TR (SC-70-5)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of MIC5365-1.2YC5-TR (SC-70-5)?
Manufactured by MICROCHIP, the MIC5365-1.2YC5-TR is housed in a SC-70-5 package with 5 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.5V to 5.5V. Key pins include: 1 (–: Multiplexed I/O & Peripheral Pin – (General)), 2 (GND: Ground Reference Pin (GND)), 3 (EN: System Enable & Hardware Reset (EN)), 4 (–: Multiplexed I/O & Peripheral Pin – (General)), 5 (–: Multiplexed I/O & Peripheral Pin – (General)).
What are the IPC-7351B PCB Footprint dimensions for MIC5365-1.2YC5-TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC5365-1.2YC5-TR (SC-70-5) has a nominal body envelope of 1.25 × 2.00 mm, pitch e = 0.65 mm, and 5 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC5365-1.2YC5-TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC5365-1.2YC5-TR (MICROCHIP, SC-70-5) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (5 pins) & MIC5365 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | – | Digital_IO | Signal terminal – (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: –. Supported peripheral buses: General. |
| 2 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 3 | EN | Digital_IO | Chip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset. |
| 4 | – | Digital_IO | Signal terminal – (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: –. Supported peripheral buses: General. |
| 5 | – | Digital_IO | Signal terminal – (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: –. Supported peripheral buses: General. |












