Mechanical Dimensions & Land Pattern (TO-263-5)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit TO-263-5 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — MIC37302WU-TR (TO-263-5)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of MIC37302WU-TR (TO-263-5)?
Manufactured by MICROCHIP, the MIC37302WU-TR is housed in a TO-263-5 package with 6 pins and a 1.70 mm lead pitch, supporting a VCC supply range of 3.0V to 2.5V. Key pins include: 1 (EN: System Enable & Hardware Reset (EN)), 2 (VIN: Regulated Power Output (VIN — 3.0V to 2.5V)), 3 (GND: Ground Reference Pin (GND)), 4 (VOUT: Regulated Power Output (VOUT — 3.0V to 2.5V)), 5 (FLG/ADJ: Multiplexed I/O & Peripheral Pin FLG/ADJ (General)), 6 (TAB: Multiplexed I/O & Peripheral Pin TAB (General)).
What are the IPC-7351B PCB Footprint dimensions for MIC37302WU-TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC37302WU-TR (TO-263-5) has a nominal body envelope of 9.00 × 10.10 mm, pitch e = 1.70 mm, and 6 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC37302WU-TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC37302WU-TR (MICROCHIP, TO-263-5) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (6 pins) & MIC37302 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | EN | Digital_IO | Chip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset. |
| 2 | VIN | Power_Out | Regulated power output rail (VIN) operating in the 3.0V to 2.5V domain (Max rating: 3.0V). |
| 3 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | VOUT | Power_Out | Regulated power output rail (VOUT) operating in the 3.0V to 2.5V domain (Max rating: 3.0V). |
| 5 | FLG/ADJ | Digital_IO | Signal terminal FLG/ADJ (I/O, 3.0V to 2.5V domain). Multiplexed alternate functions: FLG/ADJ. Supported peripheral buses: General. |
| 6 | TAB | Digital_IO | Signal terminal TAB (I/O, 3.0V to 2.5V domain). Multiplexed alternate functions: TAB. Supported peripheral buses: General. |












