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CH9114F (QFN-32-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9114F

WCHID: C46061832QFN-32-EP(4x4) · 33 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9114F (QFN-32-EP(4x4))1IO12IO233V34DTR2/ GPIO145DTR3/ GPIO206CTS3/ GPIO197RTS3/GPIO188CTS1/ GPIO79RTS1/ GPIO610CTS0/ GPIO111RTS0/ GPIO012RXD313TXD314TXD215RTS2/GPIO1216RXD217CTS2/ GPIO1333GND32TNOW0/31RI1/ TNOW1/ 30TXD129RXD128TXD027RXD026RI3/ TNOW3/ 25RESET24RI2/ TNOW2/ 23VDDK22UD+21UD-20VDD3319XO18XIGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.227.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO1I/OGeneral Purpose Digital I/O Pin IO1
2IO2I/OGeneral Purpose Digital I/O Pin IO2
33V3Power3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4DTR2/ GPIO14I/OMultiplexed I/O & Peripheral Pin DTR2/ GPIO14 (UART)
5DTR3/ GPIO20I/OMultiplexed I/O & Peripheral Pin DTR3/ GPIO20 (UART)
6CTS3/ GPIO19I/OMultiplexed I/O & Peripheral Pin CTS3/ GPIO19 (UART)
7RTS3/GPIO18I/OMultiplexed I/O & Peripheral Pin RTS3/GPIO18 (UART)
8CTS1/ GPIO7I/OMultiplexed I/O & Peripheral Pin CTS1/ GPIO7 (UART)
9RTS1/ GPIO6I/OMultiplexed I/O & Peripheral Pin RTS1/ GPIO6 (UART)
10CTS0/ GPIO1I/OMultiplexed I/O & Peripheral Pin CTS0/ GPIO1 (UART)
11RTS0/ GPIO0I/OMultiplexed I/O & Peripheral Pin RTS0/ GPIO0 (UART)
12RXD3I/OMultiplexed I/O & Peripheral Pin RXD3 (UART)
13TXD3I/OTXD3 (UART)
14TXD2I/OTXD2 (UART)
15RTS2/GPIO12I/OMultiplexed I/O & Peripheral Pin RTS2/GPIO12 (UART)
16RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
17CTS2/ GPIO13I/OMultiplexed I/O & Peripheral Pin CTS2/ GPIO13 (UART)
18XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
19XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
20VDD33PowerPower Supply Input (VDD33 — 1.2V to 3.3V)
21UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
22UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
23VDDKPowerPower Supply Input (VDDK — 1.2V to 3.3V)
24RI2/ TNOW2/ GPIO17I/OMultiplexed I/O & Peripheral Pin RI2/ TNOW2/ GPIO17 (UART)
25RESETISystem Enable & Hardware Reset (RESET)
26RI3/ TNOW3/ GPIO23I/OMultiplexed I/O & Peripheral Pin RI3/ TNOW3/ GPIO23 (UART)
27RXD0I/ORXD0 (UART)
28TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
29RXD1I/ORXD1 (UART)
30TXD1I/OTXD1 (UART)
31RI1/ TNOW1/ GPIO11I/OMultiplexed I/O & Peripheral Pin RI1/ TNOW1/ GPIO11 (UART)
32TNOW0/I/OMultiplexed I/O & Peripheral Pin TNOW0/ (General)
33GNDGNDGround Reference Pin (GND)
PIN 1 IO1
I/O
General Purpose Digital I/O Pin IO1
Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9114F (WCH · QFN-32-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9114F (QFN-32-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9114F (QFN-32-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9114F (QFN-32-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9114F (QFN-32-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-32-EP(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9114F (QFN-32-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9114F (QFN-32-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH9114
P9 · p09_fig01EXACT PACKAGE
CH9114F (QFN-32-EP(4x4)) — 7.1 QFN32 封装
7.1 QFN32 封装
P1 · p01_fig011387×530px
CH9114F (QFN-32-EP(4x4)) — 图1-1 系统框图 2、特点
图1-1 系统框图 2、特点
P2 · p02_fig011751×2301px
CH9114F (QFN-32-EP(4x4)) — CH9114 手册 https://wch.cn
CH9114 手册 https://wch.cn
P9 · p09_fig021260×955px
CH9114F (QFN-32-EP(4x4)) — 7.2 QFN56X8 封装
7.2 QFN56X8 封装
P11 · p11_fig011847×1653px
CH9114F (QFN-32-EP(4x4)) — 图8-1 高速USB 转四路TTL 串口参考电路图 +3V3 +5V Vin 2 C2 1uF LED1
图8-1 高速USB 转四路TTL 串口参考电路图 +3V3 +5V Vin 2 C2 1uF LED1
P11 · p11_fig01P11
CH9114F (QFN-32-EP(4x4)) — Datasheet Page 11 (p11_fig01)
Datasheet Page 11 (p11_fig01)

Technical Specifications & Part Details (CH9114F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9114F (QFN-32-EP(4x4)) is a 32-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.2V to 3.3V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.2V to 3.3V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-32-EP(4x4))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-32-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-32-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9114F (QFN-32-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9114F (QFN-32-EP(4x4))?

Manufactured by WCH, the CH9114F is housed in a QFN-32-EP(4x4) package with 33 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.2V to 3.3V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (DTR2/ GPIO14: Multiplexed I/O & Peripheral Pin DTR2/ GPIO14 (UART)), 5 (DTR3/ GPIO20: Multiplexed I/O & Peripheral Pin DTR3/ GPIO20 (UART)), 6 (CTS3/ GPIO19: Multiplexed I/O & Peripheral Pin CTS3/ GPIO19 (UART)).

What are the IPC-7351B PCB Footprint dimensions for CH9114F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9114F (QFN-32-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9114F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9114F (WCH, QFN-32-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & CH9114 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO1Digital_IOGeneral Purpose Digital I/O Pin IO1
2IO2Digital_IOGeneral Purpose Digital I/O Pin IO2
33V3Power_In3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4DTR2/ GPIO14Digital_IOSignal terminal DTR2/ GPIO14 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: DTR2/ GPIO14. Supported peripheral buses: UART.
5DTR3/ GPIO20Digital_IOSignal terminal DTR3/ GPIO20 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: DTR3/ GPIO20. Supported peripheral buses: UART.
6CTS3/ GPIO19Digital_IOSignal terminal CTS3/ GPIO19 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: CTS3/ GPIO19. Supported peripheral buses: UART.
7RTS3/GPIO18Digital_IOSignal terminal RTS3/GPIO18 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RTS3/GPIO18. Supported peripheral buses: UART.
8CTS1/ GPIO7Digital_IOSignal terminal CTS1/ GPIO7 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: CTS1/ GPIO7. Supported peripheral buses: UART.
9RTS1/ GPIO6Digital_IOSignal terminal RTS1/ GPIO6 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RTS1/ GPIO6. Supported peripheral buses: UART.
10CTS0/ GPIO1Digital_IOSignal terminal CTS0/ GPIO1 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: CTS0/ GPIO1. Supported peripheral buses: UART.
11RTS0/ GPIO0Digital_IOSignal terminal RTS0/ GPIO0 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RTS0/ GPIO0. Supported peripheral buses: UART.
12RXD3Digital_IOSignal terminal RXD3 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART.
13TXD3Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
14TXD2Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
15RTS2/GPIO12Digital_IOSignal terminal RTS2/GPIO12 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RTS2/GPIO12. Supported peripheral buses: UART.
16RXD2Digital_IOSignal terminal RXD2 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
17CTS2/ GPIO13Digital_IOSignal terminal CTS2/ GPIO13 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: CTS2/ GPIO13. Supported peripheral buses: UART.
18XIDigital_IOSignal terminal XI (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
19XODigital_IOSignal terminal XO (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
20VDD33Power_InPrimary positive power supply input (VDD33) operating in the 1.2V to 3.3V domain (Max rating: 3.3V).
21UD-Digital_IOSignal terminal UD- (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
22UD+Digital_IOSignal terminal UD+ (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
23VDDKPower_InPrimary positive power supply input (VDDK) operating in the 1.2V to 3.3V domain (Max rating: 3.3V).
24RI2/ TNOW2/ GPIO17Digital_IOSignal terminal RI2/ TNOW2/ GPIO17 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RI2/ TNOW2/ GPIO17. Supported peripheral buses: UART.
25RESETDigital_IOActive-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
26RI3/ TNOW3/ GPIO23Digital_IOSignal terminal RI3/ TNOW3/ GPIO23 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RI3/ TNOW3/ GPIO23. Supported peripheral buses: UART.
27RXD0Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
28TXD0Digital_IOSignal terminal TXD0 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
29RXD1Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
30TXD1Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
31RI1/ TNOW1/ GPIO11Digital_IOSignal terminal RI1/ TNOW1/ GPIO11 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RI1/ TNOW1/ GPIO11. Supported peripheral buses: UART.
32TNOW0/Digital_IOSignal terminal TNOW0/ (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: TNOW0/. Supported peripheral buses: General.
33GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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