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CH394Q (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH394Q

WCHID: C46061830LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH394Q (LQFP-48(7x7))1MDIRP2MDIRN3GND4AVDD335MDITP6MDITN7NC8AVDD339GND10NC11NC12NC13NC14GND15NC16GND17NC18NC19GND20AVDDK21VDDIO22DVDDK23NC24LED_SPD48GND47NC46NC45PMOD044PMOD143PMOD242NC41NC40NC39NC38NC37RSTB36INT35SDI34SDO33SCK32SCS31XO30XI29GND28VDDIO27LED_ACT26LED_DUP25LED_LINKGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1MDIRPI/OMultiplexed I/O & Peripheral Pin MDIRP (General)
2MDIRNI/OMultiplexed I/O & Peripheral Pin MDIRN (General)
3GNDGNDGround Reference Pin (GND)
4AVDD33PowerPower Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)
5MDITPI/OMultiplexed I/O & Peripheral Pin MDITP (General)
6MDITNI/OMultiplexed I/O & Peripheral Pin MDITN (General)
7NCI/OMultiplexed I/O & Peripheral Pin NC (General)
8AVDD33PowerPower Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)
9GNDGNDGround Reference Pin (GND)
10NCI/OMultiplexed I/O & Peripheral Pin NC (General)
11NCI/OMultiplexed I/O & Peripheral Pin NC (General)
12NCI/OMultiplexed I/O & Peripheral Pin NC (General)
13NCI/OMultiplexed I/O & Peripheral Pin NC (General)
14GNDGNDGround Reference Pin (GND)
15NCI/OMultiplexed I/O & Peripheral Pin NC (General)
16GNDGNDGround Reference Pin (GND)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18NCI/OMultiplexed I/O & Peripheral Pin NC (General)
19GNDGNDGround Reference Pin (GND)
20AVDDKPowerPower Supply Input (AVDDK — 3.3V / 5.0V Standard Logic)
21VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
22DVDDKPowerPower Supply Input (DVDDK — 3.3V / 5.0V Standard Logic)
23NCI/OMultiplexed I/O & Peripheral Pin NC (General)
24LED_SPDI/OMultiplexed I/O & Peripheral Pin LED_SPD (General)
25LED_LINKI/OMultiplexed I/O & Peripheral Pin LED_LINK (General)
26LED_DUPI/OMultiplexed I/O & Peripheral Pin LED_DUP (General)
27LED_ACTI/OMultiplexed I/O & Peripheral Pin LED_ACT (General)
28VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
29GNDGNDGround Reference Pin (GND)
30XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
31XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
32SCSI/OMultiplexed I/O & Peripheral Pin SCS (General)
33SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
34SDOI/OMultiplexed I/O & Peripheral Pin SDO (General)
35SDII/OMultiplexed I/O & Peripheral Pin SDI (General)
36INTI/OMultiplexed I/O & Peripheral Pin INT (General)
37RSTBI/OMultiplexed I/O & Peripheral Pin RSTB (General)
38NCI/OMultiplexed I/O & Peripheral Pin NC (General)
39NCI/OMultiplexed I/O & Peripheral Pin NC (General)
40NCI/OMultiplexed I/O & Peripheral Pin NC (General)
41NCI/OMultiplexed I/O & Peripheral Pin NC (General)
42NCI/OMultiplexed I/O & Peripheral Pin NC (General)
43PMOD2I/OMultiplexed I/O & Peripheral Pin PMOD2 (General)
44PMOD1I/OMultiplexed I/O & Peripheral Pin PMOD1 (General)
45PMOD0I/OMultiplexed I/O & Peripheral Pin PMOD0 (General)
46NCI/OMultiplexed I/O & Peripheral Pin NC (General)
47NCI/OMultiplexed I/O & Peripheral Pin NC (General)
48GNDGNDGround Reference Pin (GND)
PIN 1 MDIRP
I/O
Multiplexed I/O & Peripheral Pin MDIRP (General)
Design note: Signal terminal MDIRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRP. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH394Q (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH394Q (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH394Q (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH394Q (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH394Q (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH394Q (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH394Q (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH394
P3 · p03_fig01EXACT PACKAGE
CH394Q (LQFP-48(7x7)) — CH394Q 引脚号
CH394Q 引脚号
P1 · p01_fig011751×1163px
CH394Q (LQFP-48(7x7)) — 图1-1 CH394Q 应用框图
图1-1 CH394Q 应用框图
P1 · p01_fig02239×255px
CH394Q (LQFP-48(7x7)) — MDITP MDITN MDIRP MDIRN 以太网信号 MDITP MDITN MDIRP MDIRN LAM (ES
MDITP MDITN MDIRP MDIRN 以太网信号 MDITP MDITN MDIRP MDIRN LAM (ES
P38 · p38_fig011651×355px
CH394Q (LQFP-48(7x7)) — 表12-2 接收数据示例 步骤 动作 操作寄存器 地址 操作 1 获取接收到的数据的长度 Sn_RX_RS 0x0026 读出接收长度 2 获取数据在缓存区内的起始地址 Sn_RX_RD 0x0028 读出原地址A0 3 从A0取特定长度的数据L0 - A0 读数据
表12-2 接收数据示例 步骤 动作 操作寄存器 地址 操作 1 获取接收到的数据的长度 Sn_RX_RS 0x0026 读出接收长度 2 获取数据在缓存区内的起始地址 Sn_RX_RD 0x0028 读出原地址A0 3 从A0取特定长度的数据L0 - A0 读数据
P38 · p38_fig021727×555px
CH394Q (LQFP-48(7x7)) — V1.2 38
V1.2 38
P45 · p45_fig011501×624px
CH394Q (LQFP-48(7x7)) — 图12-3 硬件参考电路
图12-3 硬件参考电路
P45 · p45_fig021294×1630px
CH394Q (LQFP-48(7x7)) — 图12-3 硬件参考电路
图12-3 硬件参考电路
P45 · p45_fig02P45
CH394Q (LQFP-48(7x7)) — Datasheet Page 45 (p45_fig02)
Datasheet Page 45 (p45_fig02)

Technical Specifications & Part Details (CH394Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH394Q (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH394Q (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH394Q (LQFP-48(7x7))?

Manufactured by WCH, the CH394Q is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (MDIRP: Multiplexed I/O & Peripheral Pin MDIRP (General)), 2 (MDIRN: Multiplexed I/O & Peripheral Pin MDIRN (General)), 3 (GND: Ground Reference Pin (GND)), 4 (AVDD33: Power Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)), 5 (MDITP: Multiplexed I/O & Peripheral Pin MDITP (General)), 6 (MDITN: Multiplexed I/O & Peripheral Pin MDITN (General)).

What are the IPC-7351B PCB Footprint dimensions for CH394Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH394Q (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH394Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH394Q (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH394 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1MDIRPDigital_IOSignal terminal MDIRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRP. Supported peripheral buses: General.
2MDIRNDigital_IOSignal terminal MDIRN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRN. Supported peripheral buses: General.
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4AVDD33Power_InPrimary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5MDITPDigital_IOSignal terminal MDITP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITP. Supported peripheral buses: General.
6MDITNDigital_IOSignal terminal MDITN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITN. Supported peripheral buses: General.
7NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
8AVDD33Power_InPrimary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
10NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
11NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
12NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
16GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
17NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
19GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
20AVDDKPower_InPrimary positive power supply input (AVDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22DVDDKPower_InPrimary positive power supply input (DVDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
24LED_SPDDigital_IOSignal terminal LED_SPD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_SPD. Supported peripheral buses: General.
25LED_LINKDigital_IOSignal terminal LED_LINK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_LINK. Supported peripheral buses: General.
26LED_DUPDigital_IOSignal terminal LED_DUP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_DUP. Supported peripheral buses: General.
27LED_ACTDigital_IOSignal terminal LED_ACT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_ACT. Supported peripheral buses: General.
28VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
29GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
30XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
31XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
32SCSDigital_IOSignal terminal SCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS. Supported peripheral buses: General.
33SCKDigital_IOSignal terminal SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
34SDODigital_IOSignal terminal SDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDO. Supported peripheral buses: General.
35SDIDigital_IOSignal terminal SDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDI. Supported peripheral buses: General.
36INTDigital_IOSignal terminal INT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT. Supported peripheral buses: General.
37RSTBDigital_IOSignal terminal RSTB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTB. Supported peripheral buses: General.
38NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
39NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
40NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
41NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
42NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
43PMOD2Digital_IOSignal terminal PMOD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PMOD2. Supported peripheral buses: General.
44PMOD1Digital_IOSignal terminal PMOD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PMOD1. Supported peripheral buses: General.
45PMOD0Digital_IOSignal terminal PMOD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PMOD0. Supported peripheral buses: General.
46NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
47NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
48GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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