LQFP-32(7x7) · 32P
Synchronized Pinout (Symbol / 2D / 3D) (32/32)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 2 | PC14OSC32 IN -_ | I/O | Multiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (RTC/CLK) |
| 3 | PC15OSC32 OUT -_ | I/O | Multiplexed I/O & Peripheral Pin PC15OSC32 OUT -_ (RTC/CLK) |
| 4 | NRST | I | System Enable & Hardware Reset (NRST) |
| 5 | VDDA | Power | Power Supply Input (VDDA — 3.3V VDD (Max 4.0V)) |
| 6 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (ADC, PWM, RTC/CLK) |
| 7 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, ADC) |
| 8 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (UART, ADC) |
| 9 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (UART, ADC) |
| 10 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (SPI, ADC) |
| 11 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM) |
| 12 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC) |
| 13 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC) |
| 14 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (ADC) |
| 15 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (UART, ADC) |
| 16 | VSS | GND | Ground Reference Pin (VSS) |
| 17 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 18 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (RTC/CLK) |
| 19 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (RTC/CLK) |
| 20 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (General) |
| 21 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (SPI) |
| 22 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (SPI) |
| 23 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (SWD/JTAG) |
| 24 | PA14 | I/O | Multiplexed I/O & Peripheral Pin PA14 (UART, SWD/JTAG) |
| 25 | PA15 | I/O | Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM) |
| 26 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (SPI) |
| 27 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (SPI) |
| 28 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C) |
| 29 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (I2C) |
| 30 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (I2C) |
| 31 | BOOT0 | I | Input-Only Pin BOOT0 (General) |
| 32 | VSS | GND | Ground Reference Pin (VSS) |
PIN 1 VDD
PowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (32 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-32(7x7) · 7.00×7.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (32 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32L010
P29 · p29_fig01EXACT PACKAGE
P29 · p29_fig02EXACT PACKAGE
P83 · p83_fig01EXACT PACKAGE
P84 · p84_fig01EXACT PACKAGE
P85 · p85_fig01EXACT PACKAGE
P1 · p01_fig01881×381px
P29 · p29_fig01P29
P38 · p38_fig011546×1132px
P38 · p38_fig021546×586px
P38 · p38_fig01P38
P76 · p76_fig011546×701px
P83 · p83_fig01P83
Page 1 / 2 (15 extracted figures)
Technical Specifications & Part Details (STM32L010K8T6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32L010K8T6 (LQFP-32(7x7)) is a 32-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.8 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-32(7x7))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol32 auto-grouped pins
IPC-7351B Land Pattern32 pads · Pitch 0.80mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32L010 (3)
LQFP-32(7x7) · 32P
LQFP-32(7x7) · 32P
Mechanical Dimensions & Land Pattern (LQFP-32(7x7))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.80mm
Pad Size (W × L)Level B
0.50 × 1.20 mm
Pins / Total PadsTopology
32P / 32Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-32(7x7) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32L010K8T6 (LQFP-32(7x7))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32L010K8T6 (LQFP-32(7x7))?
Manufactured by ST, the STM32L010K8T6 is housed in a LQFP-32(7x7) package with 32 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 1.8 V to 3.6 V. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), 2 (PC14OSC32 IN -_: Multiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (RTC/CLK)), 3 (PC15OSC32 OUT -_: Multiplexed I/O & Peripheral Pin PC15OSC32 OUT -_ (RTC/CLK)), 4 (NRST: System Enable & Hardware Reset (NRST)), 5 (VDDA: Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))), 6 (PA0: Multiplexed I/O & Peripheral Pin PA0 (ADC, PWM, RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for STM32L010K8T6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L010K8T6 (LQFP-32(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.80 mm, and 32 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L010K8T6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L010K8T6 (ST, LQFP-32(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (32 pins) & STM32L010 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 2 | PC14OSC32 IN -_ | Digital_IO | Signal terminal PC14OSC32 IN -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14OSC32 IN -_. Supported peripheral buses: RTC/CLK. |
| 3 | PC15OSC32 OUT -_ | Digital_IO | Signal terminal PC15OSC32 OUT -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15OSC32 OUT -_. Supported peripheral buses: RTC/CLK. |
| 4 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 5 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 6 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: ADC, PWM, RTC/CLK. |
| 7 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC. |
| 8 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC. |
| 9 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC. |
| 10 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSUSART2CK. Supported peripheral buses: SPI, ADC. |
| 11 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCKTIM2ETR. Supported peripheral buses: SPI, ADC, PWM. |
| 12 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISOLPUART1CTS. Supported peripheral buses: SPI, ADC. |
| 13 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSIEVENTOUT. Supported peripheral buses: SPI, ADC. |
| 14 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC. |
| 15 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC. |
| 16 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 17 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 18 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: RTC/CLK. |
| 19 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: RTC/CLK. |
| 20 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General. |
| 21 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISOEVENTOUT. Supported peripheral buses: SPI. |
| 22 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSIEVENTOUT. Supported peripheral buses: SPI. |
| 23 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG. |
| 24 | PA14 | Digital_IO | Signal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: UART, SWD/JTAG. |
| 25 | PA15 | Digital_IO | Signal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSTIM2ETR. Supported peripheral buses: UART, SPI, PWM. |
| 26 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCKTIM2CH2. Supported peripheral buses: SPI. |
| 27 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISOEVENTOUT. Supported peripheral buses: SPI. |
| 28 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSILPTIM1IN1, I2C1_SMBA. Supported peripheral buses: SPI, I2C. |
| 29 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: I2C. |
| 30 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: I2C. |
| 31 | BOOT0 | Digital_IO | Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General. |
| 32 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |