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STM32WBA65CIU6 (UFQFN-48-EP) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WBA65CIU6

STID: C45616365UFQFN-48-EP · 49 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WBA65CIU6 (UFQFN-48-EP)1VSSSMPS2VDDSMPS3VLXSMPS4PB125PA86PA77PA68VDDA9PA510PA211VDD12PA113PA014PB915PB816PC15 - OSC3217PC14OSC32 IN18PC1319PB720PB621PB522VDD23PB4(NJRST)24PB3 (JTDO/TR25PA15 (JTDI)49VSS48PB1447PA946PA1045VDD1144VDD43VDDRFPA42OSC_IN41OSC_OUT40VDDRF39VDDANA38VDDHPA37RF36NRST35VDD34PH3BOOT0 -33PB1532PB031PB130PB229PA11 .28PA1227PA13 (JTMS/S26PA14 (JTCK/SGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=7.00mm · Pitch e=0.50mmD=7.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VSSSMPSGNDGround Reference Pin (VSSSMPS)
2VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
3VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
4PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
5PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, ADC, RTC/CLK)
6PA7I/OMultiplexed I/O & Peripheral Pin PA7 (UART, SPI, I2C, ADC)
7PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, I2C, ADC)
8VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
9PA5I/OMultiplexed I/O & Peripheral Pin PA5 (UART, SPI, ADC)
10PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
11VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
12PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, ADC)
13PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM)
14PB9I/OMultiplexed I/O & Peripheral Pin PB9 (UART, SPI, ADC)
15PB8I/OMultiplexed I/O & Peripheral Pin PB8 (UART, SPI, PWM)
16PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
17PC14OSC32 IN -_I/OMultiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (RTC/CLK)
18PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
19PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
20PB6I/OMultiplexed I/O & Peripheral Pin PB6 (SPI)
21PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
22VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
23PB4(NJRST)I/OMultiplexed I/O & Peripheral Pin PB4(NJRST) (UART, SPI, SWD/JTAG)
24PB3 (JTDO/TRACES WO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO/TRACES WO) (UART, I2C, SWD/JTAG)
25PA15 (JTDI)I/OMultiplexed I/O & Peripheral Pin PA15 (JTDI) (UART, SPI, I2C, SWD/JTAG)
26PA14 (JTCK/SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK/SWCLK) (UART, I2C, SWD/JTAG)
27PA13 (JTMS/SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13 (JTMS/SWDIO) (SWD/JTAG)
28PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, SPI)
29PA11 .I/OMultiplexed I/O & Peripheral Pin PA11 . (UART)
30PB2I/OMultiplexed I/O & Peripheral Pin PB2 (UART, I2C, RTC/CLK)
31PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, I2C)
32PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI)
33PB15I/OMultiplexed I/O & Peripheral Pin PB15 (UART, I2C)
34PH3BOOT0 -I/OMultiplexed I/O & Peripheral Pin PH3BOOT0 - (General)
35VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
36NRSTISystem Enable & Hardware Reset (NRST)
37RFI/OMultiplexed I/O & Peripheral Pin RF (General)
38VDDHPAPowerPower Supply Input (VDDHPA — 3.3V VDD (Max 4.0V))
39VDDANAPowerPower Supply Input (VDDANA — 3.3V VDD (Max 4.0V))
40VDDRFPowerPower Supply Input (VDDRF — 3.3V VDD (Max 4.0V))
41OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
42OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
43VDDRFPAPowerPower Supply Input (VDDRFPA — 3.3V VDD (Max 4.0V))
44VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
45VDD11PowerPower Supply Input (VDD11 — 3.3V VDD (Max 4.0V))
46PA10I/OMultiplexed I/O & Peripheral Pin PA10 (SPI)
47PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, SPI)
48PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, I2C, RTC/CLK)
49VSSGNDExposed Thermal & Ground Pad (VSS)
PIN 1 VSSSMPS
GND
Ground Reference Pin (VSSSMPS)
Design note: 0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WBA65CIU6 (ST · UFQFN-48-EP)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WBA65CIU6 (UFQFN-48-EP) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WBA65CIU6 (UFQFN-48-EP) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WBA65CIU6 (UFQFN-48-EP) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WBA65CIU6 (UFQFN-48-EP) - 4. Package Dimensions (D×E×A)
UFQFN-48-EP · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WBA65CIU6 (UFQFN-48-EP) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WBA65CIU6 (UFQFN-48-EP) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32WBA62 / STM32WBA65
P72 · p72_fig01EXACT PACKAGE
STM32WBA65CIU6 (UFQFN-48-EP) — Figure 8. UFQFPN48_USB pinout
Figure 8. UFQFPN48_USB pinout
P72 · p72_fig02EXACT PACKAGE
STM32WBA65CIU6 (UFQFN-48-EP) — Figure 9. UFQFPN48_SMPS pinout
Figure 9. UFQFPN48_SMPS pinout
P73 · p73_fig01EXACT PACKAGE
STM32WBA65CIU6 (UFQFN-48-EP) — Figure 10. UFQFPN48_SMPS_USB pinout
Figure 10. UFQFPN48_SMPS_USB pinout
P174 · p174_fig01EXACT PACKAGE
STM32WBA65CIU6 (UFQFN-48-EP) — Figure 42. UFQFPN48 - Outline D2
Figure 42. UFQFPN48 - Outline D2
P1 · p01_fig01882×815px
STM32WBA65CIU6 (UFQFN-48-EP) — • Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
• Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
P1 · p01_fig01P1
STM32WBA65CIU6 (UFQFN-48-EP) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P72 · p72_fig01P72
STM32WBA65CIU6 (UFQFN-48-EP) — Datasheet Page 72 (p72_fig01)
Datasheet Page 72 (p72_fig01)
P73 · p73_fig021546×1203px
STM32WBA65CIU6 (UFQFN-48-EP) — Figure 11. VFQFPN68_SMPS_USB pinout
Figure 11. VFQFPN68_SMPS_USB pinout
P100 · p100_fig011546×1425px
STM32WBA65CIU6 (UFQFN-48-EP) — Figure 18. Power supply scheme with LDO VDDUSB 100 nF VDDUSB
Figure 18. Power supply scheme with LDO VDDUSB 100 nF VDDUSB
P100 · p100_fig01P100
STM32WBA65CIU6 (UFQFN-48-EP) — Datasheet Page 100 (p100_fig01)
Datasheet Page 100 (p100_fig01)
P101 · p101_fig011546×1932px
STM32WBA65CIU6 (UFQFN-48-EP) — Figure 19. Power supply scheme with SMPS
Figure 19. Power supply scheme with SMPS
P102 · p102_fig011546×1842px
STM32WBA65CIU6 (UFQFN-48-EP) — Figure 20. Power supply scheme with SMPS (high RF power) VDDUSB 100 nF VDDUSB
Figure 20. Power supply scheme with SMPS (high RF power) VDDUSB 100 nF VDDUSB
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (STM32WBA65CIU6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WBA65CIU6 (UFQFN-48-EP) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SPI, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
29 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.85 mm (A1=0.05 mm)
Package family: QFN (UFQFN-48-EP)
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SPI, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.60×5.60mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFN-48-EP)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.29 × 0.80 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFN-48-EP
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WBA65CIU6 (UFQFN-48-EP)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WBA65CIU6 (UFQFN-48-EP)?

Manufactured by ST, the STM32WBA65CIU6 is housed in a UFQFN-48-EP package with 49 pins and a 0.50 mm lead pitch. Key pins include: 1 (VSSSMPS: Ground Reference Pin (VSSSMPS)), 2 (VDDSMPS: Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))), 3 (VLXSMPS: Multiplexed I/O & Peripheral Pin VLXSMPS (General)), 4 (PB12: Multiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)), 5 (PA8: Multiplexed I/O & Peripheral Pin PA8 (UART, SPI, ADC, RTC/CLK)), 6 (PA7: Multiplexed I/O & Peripheral Pin PA7 (UART, SPI, I2C, ADC)).

What are the IPC-7351B PCB Footprint dimensions for STM32WBA65CIU6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WBA65CIU6 (UFQFN-48-EP) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.60 × 5.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WBA65CIU6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WBA65CIU6 (ST, UFQFN-48-EP) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & STM32WBA62 / STM32WBA65 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
2VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
3VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
4PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI, I2C.
5PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_RDY. Supported peripheral buses: UART, SPI, ADC, RTC/CLK.
6PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI3_SCKUSART1CTS. Supported peripheral buses: UART, SPI, I2C, ADC.
7PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI3_RDY. Supported peripheral buses: UART, SPI, I2C, ADC.
8VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
9PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: UART, SPI, ADC.
10PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
11VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
12PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI, ADC.
13PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM.
14PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI, ADC.
15PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI_TSCG2IO4. Supported peripheral buses: UART, SPI, PWM.
16PC15 - OSC32_OUTDigital_IOSignal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK.
17PC14OSC32 IN -_Digital_IOSignal terminal PC14OSC32 IN -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14OSC32 IN -_. Supported peripheral buses: RTC/CLK.
18PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
19PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
20PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: SPI.
21PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
22VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
23PB4(NJRST)Digital_IOSignal terminal PB4(NJRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, SWD/JTAG.
24PB3 (JTDO/TRACES WO)Digital_IOSignal terminal PB3 (JTDO/TRACES WO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB3 (JTDO/TRACES WO). Supported peripheral buses: UART, I2C, SWD/JTAG.
25PA15 (JTDI)Digital_IOSignal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL, SPI1_MOSI_USART3RTSDE. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG.
26PA14 (JTCK/SWCLK)Digital_IOSignal terminal PA14 (JTCK/SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SMBA. Supported peripheral buses: UART, I2C, SWD/JTAG.
27PA13 (JTMS/SWDIO)Digital_IOSignal terminal PA13 (JTMS/SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS/SWDIO). Supported peripheral buses: SWD/JTAG.
28PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS_TSCG3IO4. Supported peripheral buses: UART, SPI.
29PA11 .Digital_IOSignal terminal PA11 . (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11 .. Supported peripheral buses: UART.
30PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: UART, I2C, RTC/CLK.
31PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA. Supported peripheral buses: UART, I2C.
32PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI_USART3CKEVENTOUT. Supported peripheral buses: UART, SPI.
33PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: UART, I2C.
34PH3BOOT0 -Digital_IOSignal terminal PH3BOOT0 - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH3BOOT0 -. Supported peripheral buses: General.
35VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
36NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
37RFRF_50OhmSignal terminal RF (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RF. Supported peripheral buses: General.
38VDDHPAPower_InPrimary positive power supply input (VDDHPA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
39VDDANAPower_InPrimary positive power supply input (VDDANA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
40VDDRFPower_InPrimary positive power supply input (VDDRF) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
41OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
42OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
43VDDRFPAPower_InPrimary positive power supply input (VDDRFPA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
44VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
45VDD11Power_InPrimary positive power supply input (VDD11) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
46PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSLPUART1RX. Supported peripheral buses: SPI.
47PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOSPI2SCK. Supported peripheral buses: UART, SPI.
48PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: UART, I2C, RTC/CLK.
49VSSGNDBottom exposed die attach pad (VSS) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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