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C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL) — Symbol, Footprint IPC-7351B & 3D STEP Model

C45066894

SemiconductorWLCSP-68_L3.2-W3.1-P0.30-TL · 68 Pins · Pitch 0.35mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL)A1VDDUSBA3PG10A5VDDIO2A7PB7A9VDDB2VDDB4PG14B6PB4B8PH3-BOOT0C1PA12C3PG9C5VSSC7PB6C9VBATD2VSSD4PG12D6PB3D8VSSE1PA11E3PA15E5PG13E7PB5E9PC14-OSC32_IF2PA10F4PA14F6PG15F8PC13G1VDDIO2G3PA9G5PG11G7NRSTG9PC15-OSC32_OH2VSSH4PA13R9VDDR7PA6R5PB2R3VDDSMPSR1VDDP8VSSP6PB1P4VLXSMPSP2VDD11N9PA3N7PA4N5PB0N3VSSSMPSN1VSSM8PA2M6PA7M4PB13M2PB14L9VDDAL7PA1L5PG3L3PB15L1PG2K8VSSAK6PA5K4PG5K2PG4J9PH0-OSC_INJ7PA0J5PG8J3PG7J1PG6H8PH1-OSC_OUTH6PA8Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.248.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3mm
2. 2D FOOTPRINT
A1C1E1G1J1L1N1R1B2D2F2H2K2M2P2A3C3E3G3J3L3N3R3B4D4F4H4K4M4P4A5C5E5G5J5L5N5R5B6D6F6H6K6M6P6A7C7E7G7J7L7N7R7B8D8F8H8K8M8P8A9C9E9G9J9L9N9R9E=3.20mm · Pitch e=0.35mmD=3.10mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 3.20mm × 3.10mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (68/68)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VDDUSBPowerPower Supply Input (VDDUSB — 3.3V / 5.0V Standard Logic)
A3PG10I/OMultiplexed I/O & Peripheral Pin PG10 (General)
A5VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V / 5.0V Standard Logic)
A7PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
A9VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
B2VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
B4PG14I/OMultiplexed I/O & Peripheral Pin PG14 (General)
B6PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
B8PH3-BOOT0I/OMultiplexed I/O & Peripheral Pin PH3-BOOT0 (General)
C1PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
C3PG9I/OMultiplexed I/O & Peripheral Pin PG9 (General)
C5VSSGNDGround Reference Pin (VSS)
C7PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
C9VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
D2VSSGNDGround Reference Pin (VSS)
D4PG12I/OMultiplexed I/O & Peripheral Pin PG12 (General)
D6PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
D8VSSGNDGround Reference Pin (VSS)
E1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
E3PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
E5PG13I/OMultiplexed I/O & Peripheral Pin PG13 (General)
E7PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
E9PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
F2PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
F4PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
F6PG15I/OMultiplexed I/O & Peripheral Pin PG15 (General)
F8PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
G1VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V / 5.0V Standard Logic)
G3PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
G5PG11I/OMultiplexed I/O & Peripheral Pin PG11 (General)
G7NRSTISystem Enable & Hardware Reset (NRST)
G9PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
H2VSSGNDGround Reference Pin (VSS)
H4PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
H6PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
H8PH1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)
J1PG6I/OMultiplexed I/O & Peripheral Pin PG6 (General)
J3PG7I/OMultiplexed I/O & Peripheral Pin PG7 (General)
J5PG8I/OMultiplexed I/O & Peripheral Pin PG8 (General)
J7PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
J9PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
K2PG4I/OMultiplexed I/O & Peripheral Pin PG4 (General)
K4PG5I/OMultiplexed I/O & Peripheral Pin PG5 (General)
K6PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
K8VSSAGNDGround Reference Pin (VSSA)
L1PG2I/OMultiplexed I/O & Peripheral Pin PG2 (General)
L3PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
L5PG3I/OMultiplexed I/O & Peripheral Pin PG3 (General)
L7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
L9VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
M2PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
M4PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
M6PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
M8PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
N1VSSGNDGround Reference Pin (VSS)
N3VSSSMPSGNDGround Reference Pin (VSSSMPS)
N5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
N7PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
N9PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
P2VDD11PowerPower Supply Input (VDD11 — 3.3V / 5.0V Standard Logic)
P4VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
P6PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
P8VSSGNDGround Reference Pin (VSS)
R1VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
R3VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V / 5.0V Standard Logic)
R5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
R7PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
R9VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
PIN A1 VDDUSB
Power
Power Supply Input (VDDUSB — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDDUSB) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C45066894 (Semiconductor · WLCSP-68_L3.2-W3.1-P0.30-TL)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL) - 2. Standard Pinout (Top View)
True package pinout (68 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL) - 4. Package Dimensions (D×E×A)
WLCSP-68_L3.2-W3.1-P0.30-TL · 3.20×3.10mm · Pitch 0.35mmExpand ›
5. Recommended Land PatternLAND PATTERN
C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL) - 5. Recommended Land Pattern
IPC-7351B Footprint (68 Pads)Expand ›
6. Application SchematicSCHEMATIC
C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C45066894)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL) is a 68-pin standard electronic & interconnect component featuring a 3.10 × 3.20 × 0.55 mm mechanical envelope (lead pitch e = 0.35 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.10 × 3.20 × 0.55 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-68_L3.2-W3.1-P0.30-TL)
Pin Count & Lead PitchN / e
68 Pins | Pitch e = 0.35 mm (13.8 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol68 auto-grouped pins
OK
IPC-7351B Land Pattern68 pads · Pitch 0.35mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-68_L3.2-W3.1-P0.30-TL)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.10 × 3.20 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.35mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
68P / 68Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-68_L3.2-W3.1-P0.30-TL
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL)?

Manufactured by Semiconductor, the C45066894 is housed in a WLCSP-68_L3.2-W3.1-P0.30-TL package with 68 pins and a 0.35 mm lead pitch. Key pins include: A1 (VDDUSB: Power Supply Input (VDDUSB — 3.3V / 5.0V Standard Logic)), A3 (PG10: Multiplexed I/O & Peripheral Pin PG10 (General)), A5 (VDDIO2: Power Supply Input (VDDIO2 — 3.3V / 5.0V Standard Logic)), A7 (PB7: Multiplexed I/O & Peripheral Pin PB7 (General)), A9 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), B2 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for C45066894?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C45066894 (WLCSP-68_L3.2-W3.1-P0.30-TL) has a nominal body envelope of 3.20 × 3.10 mm, pitch e = 0.35 mm, and 68 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C45066894?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C45066894 (Semiconductor, WLCSP-68_L3.2-W3.1-P0.30-TL) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (68 pins) & STM32U375 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
A3PG10Digital_IOSignal terminal PG10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG10. Supported peripheral buses: General.
A5VDDIO2Power_InPrimary positive power supply input (VDDIO2) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
A7PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
A9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B4PG14Digital_IOSignal terminal PG14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG14. Supported peripheral buses: General.
B6PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
B8PH3-BOOT0Digital_IOSignal terminal PH3-BOOT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH3-BOOT0. Supported peripheral buses: General.
C1PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
C3PG9Digital_IOSignal terminal PG9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG9. Supported peripheral buses: General.
C5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C7PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
C9VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D4PG12Digital_IOSignal terminal PG12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG12. Supported peripheral buses: General.
D6PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
D8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
E3PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
E5PG13Digital_IOSignal terminal PG13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG13. Supported peripheral buses: General.
E7PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
E9PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
F2PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
F4PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
F6PG15Digital_IOSignal terminal PG15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG15. Supported peripheral buses: General.
F8PC13Digital_IOSignal terminal PC13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
G1VDDIO2Power_InPrimary positive power supply input (VDDIO2) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
G3PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
G5PG11Digital_IOSignal terminal PG11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG11. Supported peripheral buses: General.
G7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
G9PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
H2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
H4PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
H6PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
H8PH1-OSC_OUTDigital_IOSignal terminal PH1-OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH1-OSC_OUT. Supported peripheral buses: RTC/CLK.
J1PG6Digital_IOSignal terminal PG6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG6. Supported peripheral buses: General.
J3PG7Digital_IOSignal terminal PG7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG7. Supported peripheral buses: General.
J5PG8Digital_IOSignal terminal PG8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG8. Supported peripheral buses: General.
J7PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
J9PH0-OSC_INDigital_IOSignal terminal PH0-OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK.
K2PG4Digital_IOSignal terminal PG4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG4. Supported peripheral buses: General.
K4PG5Digital_IOSignal terminal PG5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG5. Supported peripheral buses: General.
K6PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
K8VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
L1PG2Digital_IOSignal terminal PG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG2. Supported peripheral buses: General.
L3PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
L5PG3Digital_IOSignal terminal PG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG3. Supported peripheral buses: General.
L7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
L9VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
M2PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
M4PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
M6PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
M8PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
N1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
N3VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
N5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
N7PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
N9PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
P2VDD11Power_InPrimary positive power supply input (VDD11) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
P4VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
P6PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
P8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
R1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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