UFQFN-48 · 49P
IPC-7351B
49P7.0×7.0×0.85mmP=0.5mm
STM32WBA62 / STM32WBA65 (UFQFN-48)
Synchronized Pinout (Symbol / 2D / 3D) (49/49)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | VSSSMPS | GND | Ground Reference Pin (VSSSMPS) |
| 2 | VDDSMPS | Power | Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V)) |
| 3 | VLXSMPS | I/O | Multiplexed I/O & Peripheral Pin VLXSMPS (General) |
| 4 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C) |
| 5 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (UART, SPI, ADC, RTC/CLK) |
| 6 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (UART, SPI, I2C, ADC) |
| 7 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (UART, SPI, I2C, ADC) |
| 8 | VDDA | Power | Power Supply Input (VDDA — 3.3V VDD (Max 4.0V)) |
| 9 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (UART, SPI, ADC) |
| 10 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM) |
| 11 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 12 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, SPI, ADC) |
| 13 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM) |
| 14 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (UART, SPI, ADC) |
| 15 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (UART, SPI, PWM) |
| 16 | PC15 - OSC32_OUT | I/O | Multiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK) |
| 17 | PC14OSC32 IN -_ | I/O | Multiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (RTC/CLK) |
| 18 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| 19 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (General) |
| 20 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (SPI) |
| 21 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (General) |
| 22 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 23 | PB4(NJRST) | I/O | Multiplexed I/O & Peripheral Pin PB4(NJRST) (UART, SPI, SWD/JTAG) |
| 24 | PB3 (JTDO/TRACES WO) | I/O | Multiplexed I/O & Peripheral Pin PB3 (JTDO/TRACES WO) (UART, I2C, SWD/JTAG) |
| 25 | PA15 (JTDI) | I/O | Multiplexed I/O & Peripheral Pin PA15 (JTDI) (UART, SPI, I2C, SWD/JTAG) |
| 26 | PA14 (JTCK/SWCLK) | I/O | Multiplexed I/O & Peripheral Pin PA14 (JTCK/SWCLK) (UART, I2C, SWD/JTAG) |
| 27 | PA13 (JTMS/SWDIO) | I/O | Multiplexed I/O & Peripheral Pin PA13 (JTMS/SWDIO) (SWD/JTAG) |
| 28 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (UART, SPI) |
| 29 | PA11 . | I/O | Multiplexed I/O & Peripheral Pin PA11 . (UART) |
| 30 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (UART, I2C, RTC/CLK) |
| 31 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (UART, I2C) |
| 32 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (UART, SPI) |
| 33 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (UART, I2C) |
| 34 | PH3BOOT0 - | I/O | Multiplexed I/O & Peripheral Pin PH3BOOT0 - (General) |
| 35 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 36 | NRST | I | System Enable & Hardware Reset (NRST) |
| 37 | RF | I/O | Multiplexed I/O & Peripheral Pin RF (General) |
| 38 | VDDHPA | Power | Power Supply Input (VDDHPA — 3.3V VDD (Max 4.0V)) |
| 39 | VDDANA | Power | Power Supply Input (VDDANA — 3.3V VDD (Max 4.0V)) |
| 40 | VDDRF | Power | Power Supply Input (VDDRF — 3.3V VDD (Max 4.0V)) |
| 41 | OSC_OUT | I/O | Multiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK) |
| 42 | OSC_IN | I/O | Multiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK) |
| 43 | VDDRFPA | Power | Power Supply Input (VDDRFPA — 3.3V VDD (Max 4.0V)) |
| 44 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 45 | VDD11 | Power | Power Supply Input (VDD11 — 3.3V VDD (Max 4.0V)) |
| 46 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (SPI) |
| 47 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (UART, SPI) |
| 48 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (UART, I2C, RTC/CLK) |
| 49 | VSS | GND | Exposed Thermal & Ground Pad (VSS) |
PIN 1 VSSSMPS
GNDGround Reference Pin (VSSSMPS)
Design note: 0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
UFQFN-48 · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for STM32WBA62 / STM32WBA65
P72 · p72_fig01EXACT PACKAGE
P72 · p72_fig02EXACT PACKAGE
P73 · p73_fig01EXACT PACKAGE
P174 · p174_fig01EXACT PACKAGE
P1 · p01_fig01882×815px
P73 · p73_fig021546×1203px
P100 · p100_fig011546×1425px
P100 · p100_fig01P100
P101 · p101_fig011546×1932px
P102 · p102_fig011546×1842px
P155 · p155_fig011547×755px
P178 · p178_fig011559×876px
Technical Specifications & Part Details (STM32WBA62CIU6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32WBA62CIU6 (UFQFN-48) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SPI, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
29 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.85 mm (A1=0.05 mm)
Package family: QFN (UFQFN-48)
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SPI, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol49 auto-grouped pins
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 5.60×5.60mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32WBA62 / STM32WBA65 (2)
UFQFN-48-EP · 49P
IPC-7351B
49P7.0×7.0×0.85mmP=0.5mm
STM32WBA62 / STM32WBA65 (UFQFN-48-EP)
Mechanical Dimensions & Land Pattern (UFQFN-48)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.29 × 0.80 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit UFQFN-48 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32WBA62CIU6 (UFQFN-48)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32WBA62CIU6 (UFQFN-48)?
Manufactured by ST, the STM32WBA62CIU6 is housed in a UFQFN-48 package with 49 pins and a 0.50 mm lead pitch. Key pins include: 1 (VSSSMPS: Ground Reference Pin (VSSSMPS)), 2 (VDDSMPS: Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))), 3 (VLXSMPS: Multiplexed I/O & Peripheral Pin VLXSMPS (General)), 4 (PB12: Multiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)), 5 (PA8: Multiplexed I/O & Peripheral Pin PA8 (UART, SPI, ADC, RTC/CLK)), 6 (PA7: Multiplexed I/O & Peripheral Pin PA7 (UART, SPI, I2C, ADC)).
What are the IPC-7351B PCB Footprint dimensions for STM32WBA62CIU6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WBA62CIU6 (UFQFN-48) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.60 × 5.60 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WBA62CIU6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WBA62CIU6 (ST, UFQFN-48) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (49 pins) & STM32WBA62 / STM32WBA65 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VSSSMPS | GND | 0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 2 | VDDSMPS | Power_In | Primary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 3 | VLXSMPS | Digital_IO | Signal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General. |
| 4 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI, I2C. |
| 5 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_RDY. Supported peripheral buses: UART, SPI, ADC, RTC/CLK. |
| 6 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI3_SCKUSART1CTS. Supported peripheral buses: UART, SPI, I2C, ADC. |
| 7 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI3_RDY. Supported peripheral buses: UART, SPI, I2C, ADC. |
| 8 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 9 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: UART, SPI, ADC. |
| 10 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM. |
| 11 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 12 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI, ADC. |
| 13 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM. |
| 14 | PB9 | Digital_IO | Signal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI, ADC. |
| 15 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI_TSCG2IO4. Supported peripheral buses: UART, SPI, PWM. |
| 16 | PC15 - OSC32_OUT | Digital_IO | Signal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK. |
| 17 | PC14OSC32 IN -_ | Digital_IO | Signal terminal PC14OSC32 IN -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14OSC32 IN -_. Supported peripheral buses: RTC/CLK. |
| 18 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| 19 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General. |
| 20 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: SPI. |
| 21 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General. |
| 22 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 23 | PB4(NJRST) | Digital_IO | Signal terminal PB4(NJRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, SWD/JTAG. |
| 24 | PB3 (JTDO/TRACES WO) | Digital_IO | Signal terminal PB3 (JTDO/TRACES WO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB3 (JTDO/TRACES WO). Supported peripheral buses: UART, I2C, SWD/JTAG. |
| 25 | PA15 (JTDI) | Digital_IO | Signal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL, SPI1_MOSI_USART3RTSDE. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG. |
| 26 | PA14 (JTCK/SWCLK) | Digital_IO | Signal terminal PA14 (JTCK/SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SMBA. Supported peripheral buses: UART, I2C, SWD/JTAG. |
| 27 | PA13 (JTMS/SWDIO) | Digital_IO | Signal terminal PA13 (JTMS/SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS/SWDIO). Supported peripheral buses: SWD/JTAG. |
| 28 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS_TSCG3IO4. Supported peripheral buses: UART, SPI. |
| 29 | PA11 . | Digital_IO | Signal terminal PA11 . (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11 .. Supported peripheral buses: UART. |
| 30 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: UART, I2C, RTC/CLK. |
| 31 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA. Supported peripheral buses: UART, I2C. |
| 32 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI_USART3CKEVENTOUT. Supported peripheral buses: UART, SPI. |
| 33 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: UART, I2C. |
| 34 | PH3BOOT0 - | Digital_IO | Signal terminal PH3BOOT0 - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH3BOOT0 -. Supported peripheral buses: General. |
| 35 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 36 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 37 | RF | RF_50Ohm | Signal terminal RF (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RF. Supported peripheral buses: General. |
| 38 | VDDHPA | Power_In | Primary positive power supply input (VDDHPA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 39 | VDDANA | Power_In | Primary positive power supply input (VDDANA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 40 | VDDRF | Power_In | Primary positive power supply input (VDDRF) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 41 | OSC_OUT | Digital_IO | Signal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK. |
| 42 | OSC_IN | Digital_IO | Signal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK. |
| 43 | VDDRFPA | Power_In | Primary positive power supply input (VDDRFPA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 44 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 45 | VDD11 | Power_In | Primary positive power supply input (VDD11) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 46 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSLPUART1RX. Supported peripheral buses: SPI. |
| 47 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOSPI2SCK. Supported peripheral buses: UART, SPI. |
| 48 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: UART, I2C, RTC/CLK. |
| 49 | VSS | GND | Bottom exposed die attach pad (VSS) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |