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STM32C091ECY6TR (WLCSP-24) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32C091ECY6TR

STID: C44847700WLCSP-24 · 24 Pins · Pitch 0.31mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32C091ECY6TR (WLCSP-24)A1PA15A3PB5A5PB6A7PC14-OSCX_INB2PA14BOOT0 -B4PB8B6PC15-OSCX_OUC1PB1C3PA13C5PA0C7VDDD2PA4G7PA2G5PA5G3PA7G1PA8F6PA3F4PA6F2PA11[PA9]E7PF2NRST -E5PA1E3PB0E1PA12[PA10]D6VSSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.820.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
A1A3A5A7B2B4B6C1C3C5C7D2D6E1E3E5E7F2F4F6G1G3G5G7E=1.70mm · Pitch e=0.31mmD=2.60mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 1.70mm × 2.60mm · Pitch: 0.31mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (24/24)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)
A3PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C, PWM)
A5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, SPI, I2C, PWM)
A7PC14-OSCX_INI/OMultiplexed I/O & Peripheral Pin PC14-OSCX_IN (RTC/CLK)
B2PA14BOOT0 -I/OMultiplexed I/O & Peripheral Pin PA14BOOT0 - (UART, SPI, ADC, PWM, SWD/JTAG)
B4PB8I/OMultiplexed I/O & Peripheral Pin PB8 (UART, SPI, I2C)
B6PC15-OSCX_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSCX_OUT (RTC/CLK)
C1PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
C3PA13I/OMultiplexed I/O & Peripheral Pin PA13 (UART, ADC, SWD/JTAG)
C5PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM)
C7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D2PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC, RTC/CLK)
D6VSSGNDGround Reference Pin (VSS)
E1PA12[PA10]I/OMultiplexed I/O & Peripheral Pin PA12[PA10] (UART, SPI, I2C)
E3PB0I/OMultiplexed I/O & Peripheral Pin PB0 (SPI, ADC)
E5PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, I2C, ADC, PWM)
E7PF2NRST -I/OMultiplexed I/O & Peripheral Pin PF2NRST - (RTC/CLK)
F2PA11[PA9]I/OMultiplexed I/O & Peripheral Pin PA11[PA9] (UART, SPI)
F4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
F6PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, SPI, ADC)
G1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, ADC, PWM, RTC/CLK)
G3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, I2C, ADC)
G5PA5I/OMultiplexed I/O & Peripheral Pin PA5 (UART, SPI, ADC, PWM)
G7PA2I/OMultiplexed I/O & Peripheral Pin PA2 (SPI, ADC, PWM)
PIN A1 PA15
I/O
Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)
Design note: Alt: SPI1 NSS/I2S1_WSUSART2RX_ ,_ , TIM1_CH1MCO2 , , USART1 RTS/USART1 DE/USART1_CK__ , TIM2 CH1/TIM2_ETR_ , USART4 RTS/USART4 DE/USART4_CK__ , EVENTOUT , USART3 RTS/USART3 DE/USART3_CK__
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32C091ECY6TR (ST · WLCSP-24)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32C091ECY6TR (WLCSP-24) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32C091ECY6TR (WLCSP-24) - 2. Standard Pinout (Top View)
True package pinout (24 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32C091ECY6TR (WLCSP-24) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32C091ECY6TR (WLCSP-24) - 4. Package Dimensions (D×E×A)
WLCSP-24 · 1.70×2.60mm · Pitch 0.31mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32C091ECY6TR (WLCSP-24) - 5. Recommended Land Pattern
IPC-7351B Footprint (24 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32C091ECY6TR (WLCSP-24) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)
Showing 1–12 of 17 uncropped original figures for STM32C091 / STM32C092
P29 · p29_fig01EXACT PACKAGE
STM32C091ECY6TR (WLCSP-24) — Figure 3. STM32C09xFxP TSSOP20 pinout
Figure 3. STM32C09xFxP TSSOP20 pinout
P29 · p29_fig02EXACT PACKAGE
STM32C091ECY6TR (WLCSP-24) — Figure 4. STM32C09xExY WLCSP24 ballout
Figure 4. STM32C09xExY WLCSP24 ballout
P95 · p95_fig01EXACT PACKAGE
STM32C091ECY6TR (WLCSP-24) — Figure 36. WLCSP24 - Outline
Figure 36. WLCSP24 - Outline
P1 · p01_fig01883×589px
STM32C091ECY6TR (WLCSP-24) — STM32C092xB/xC Arm®Cortex®-M0+ 32-bit MCU, 256 KB flash, 36 KB RAM,
STM32C092xB/xC Arm®Cortex®-M0+ 32-bit MCU, 256 KB flash, 36 KB RAM,
P1 · p01_fig02196×196px
STM32C091ECY6TR (WLCSP-24) — (4 × 4 mm)
(4 × 4 mm)
P1 · p01_fig02P1
STM32C091ECY6TR (WLCSP-24) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P30 · p30_fig011546×707px
STM32C091ECY6TR (WLCSP-24) — Figure 5. STM32C09xGxU UFQFPN28 pinout Top view
Figure 5. STM32C09xGxU UFQFPN28 pinout Top view
P30 · p30_fig021546×761px
STM32C091ECY6TR (WLCSP-24) — Figure 6. STM32C09xKxT LQFP32 pinout
Figure 6. STM32C09xKxT LQFP32 pinout
P30 · p30_fig031546×796px
STM32C091ECY6TR (WLCSP-24) — Figure 7. STM32C09xKxU UFQFPN32 pinout
Figure 7. STM32C09xKxU UFQFPN32 pinout
P31 · p31_fig011546×930px
STM32C091ECY6TR (WLCSP-24) — Figure 8. STM32C09xCxT LQFP48 pinout
Figure 8. STM32C09xCxT LQFP48 pinout
P31 · p31_fig021546×918px
STM32C091ECY6TR (WLCSP-24) — Figure 9. STM32C09xCxU UFQFPN48 pinout
Figure 9. STM32C09xCxU UFQFPN48 pinout
P46 · p46_fig011546×1119px
STM32C091ECY6TR (WLCSP-24) — Figure 14. Power supply scheme
Figure 14. Power supply scheme
Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (STM32C091ECY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32C091ECY6TR (WLCSP-24) is a 24-pin embedded microcontroller unit (mcu) featuring a 2.61 × 1.73 × 0.55 mm mechanical envelope (lead pitch e = 0.35 mm). Rated for 2.0 V to 3.6 V supply operation across -40°C to 85°C with integrated UART, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
2.0 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
20 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
2.61 × 1.73 × 0.55 mm (A1=0.04 mm)
Package family: OTHER (WLCSP-24)
Pin Count & Lead PitchN / e
24 Pins | Pitch e = 0.35 mm (13.8 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PA14BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol24 auto-grouped pins
OK
IPC-7351B Land Pattern24 pads · Pitch 0.31mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-24)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.60 × 1.70 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.31mm
Pad Size (W × L)Level B
0.16 × 0.16 mm
Pins / Total PadsTopology
24P / 24Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-24
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32C091ECY6TR (WLCSP-24)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32C091ECY6TR (WLCSP-24)?

Manufactured by ST, the STM32C091ECY6TR is housed in a WLCSP-24 package with 24 pins and a 0.31 mm lead pitch, supporting a VCC supply range of 2.0 V to 3.6 V. Key pins include: A1 (PA15: Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)), A3 (PB5: Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C, PWM)), A5 (PB6: Multiplexed I/O & Peripheral Pin PB6 (UART, SPI, I2C, PWM)), A7 (PC14-OSCX_IN: Multiplexed I/O & Peripheral Pin PC14-OSCX_IN (RTC/CLK)), B2 (PA14BOOT0 -: Multiplexed I/O & Peripheral Pin PA14BOOT0 - (UART, SPI, ADC, PWM, SWD/JTAG)), B4 (PB8: Multiplexed I/O & Peripheral Pin PB8 (UART, SPI, I2C)).

What are the IPC-7351B PCB Footprint dimensions for STM32C091ECY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32C091ECY6TR (WLCSP-24) has a nominal body envelope of 1.70 × 2.60 mm, pitch e = 0.31 mm, and 24 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32C091ECY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32C091ECY6TR (ST, WLCSP-24) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (24 pins) & STM32C091 / STM32C092 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, PWM.
A3PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C1_SMBA. Supported peripheral buses: SPI, I2C, PWM.
A5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, SPI1_MISO, SPI1_SCK. Supported peripheral buses: UART, SPI, I2C, PWM.
A7PC14-OSCX_INDigital_IOSignal terminal PC14-OSCX_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSCX_IN. Supported peripheral buses: RTC/CLK.
B2PA14BOOT0 -Digital_IOSignal terminal PA14BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, PWM, SWD/JTAG.
B4PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKTIM15BKIN. Supported peripheral buses: UART, SPI, I2C.
B6PC15-OSCX_OUTDigital_IOSignal terminal PC15-OSCX_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSCX_OUT. Supported peripheral buses: RTC/CLK.
C1PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
C3PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: UART, ADC, SWD/JTAG.
C5PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, ADC, PWM.
C7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D2PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI2_MOSITIM14CH1. Supported peripheral buses: SPI, ADC, RTC/CLK.
D6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E1PA12[PA10]Digital_IOSignal terminal PA12[PA10] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C2_SDA. Supported peripheral buses: UART, SPI, I2C.
E3PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, ADC.
E5PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, I2C, ADC, PWM.
E7PF2NRST -Digital_IOSignal terminal PF2NRST - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF2NRST -. Supported peripheral buses: RTC/CLK.
F2PA11[PA9]Digital_IOSignal terminal PA11[PA9] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI.
F4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC.
F6PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, ADC.
G1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, SPI2_MISOEVENTOUT, SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, PWM, RTC/CLK.
G3PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C2_SCL. Supported peripheral buses: SPI, I2C, ADC.
G5PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, ADC, PWM.
G7PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
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