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STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L476JEY6TR

STID: C443973WLCSP-72(3.8x4.4) · 72 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L476JEY6TR (WLCSP-72(3.8x4.4))A1VDDUSBA2PA15A3PD2A4PG9A5PG14A6PB3A7PB7A8VSSA9VDDB1VSSB2PA14B3PC12B4PG10B5PG13B6VDDIO2B7PB6B8PC13B9VBATC1PA12C2PA13C3PC11C4PG11C5PG12C6PB4C7PB5C8IOC8C9PC14 - OSC32D1PA11D2PA10D3PC10D7BOOT0D8PH1 - OSC_ OD9PH0 - OSC_INE1PC9E2PA8E3PA9J9VSSJ8VDDJ7PC4J6PC5J5PB0J4PB1J3PB2J2VSSJ1VDDH9VDDAH8PA0H7PA3H6PA5H5PA6H4PA7H3PB10H2PB13H1PB12G9VSSA/ VREF -G8VREF+G7PC3G6PA2G5PA4G4PA1G3PB11G2PB14G1PB15F9PC0F8PC1F7PC2F3PC6F2PC8F1PC7E9NRSTE8PB9E7PB8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.850.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8A9B1B2B3B4B5B6B7B8B9C1C2C3C4C5C6C7C8C9D1D2D3D7D8D9E1E2E3E7E8E9F1F2F3F7F8F9G1G2G3G4G5G6G7G8G9H1H2H3H4H5H6H7H8H9J1J2J3J4J5J6J7J8J9E=4.40mm · Pitch e=0.40mmD=3.80mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.40mm × 3.80mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (72/72)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
A2PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
A3PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
A4PG9I/OMultiplexed I/O & Peripheral Pin PG9 (General)
A5PG14I/OMultiplexed I/O & Peripheral Pin PG14 (General)
A6PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
A7PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
A8VSSGNDGround Reference Pin (VSS)
A9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B1VSSGNDGround Reference Pin (VSS)
B2PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
B3PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
B4PG10I/OMultiplexed I/O & Peripheral Pin PG10 (General)
B5PG13I/OMultiplexed I/O & Peripheral Pin PG13 (General)
B6VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
B7PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
B8PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
B9VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C1PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
C2PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
C3PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
C4PG11I/OMultiplexed I/O & Peripheral Pin PG11 (General)
C5PG12I/OMultiplexed I/O & Peripheral Pin PG12 (General)
C6PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
C7PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
C8IOC8I/OGeneral Purpose Digital I/O Pin IOC8
C9PC14 - OSC32_ IN(PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_ IN(PC14) (RTC/CLK)
D1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
D2PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
D3PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
D7BOOT0IInput-Only Pin BOOT0 (General)
D8PH1 - OSC_ OUT (PH1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC_ OUT (PH1) (RTC/CLK)
D9PH0 - OSC_IN (PH0)I/OMultiplexed I/O & Peripheral Pin PH0 - OSC_IN (PH0) (RTC/CLK)
E1PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E2PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
E3PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
E7PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
E8PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
E9NRSTISystem Enable & Hardware Reset (NRST)
F1PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
F2PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F3PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
F7PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
F8PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
F9PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
G1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
G2PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
G3PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
G4PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
G5PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
G6PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
G7PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, I2C, ADC)
G8VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
G9VSSA/ VREF -GNDGround Reference Pin (VSSA/ VREF -)
H1PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
H2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
H3PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
H4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (ADC, PWM)
H5PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, ADC)
H6PA5I/OMultiplexed I/O & Peripheral Pin PA5 (ADC, DAC, PWM)
H7PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
H8PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
H9VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
J1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J2VSSGNDGround Reference Pin (VSS)
J3PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
J4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
J5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM)
J6PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
J7PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
J8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J9VSSGNDGround Reference Pin (VSS)
PIN A1 VDDUSB
Power
Power Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 32 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L476JEY6TR (ST · WLCSP-72(3.8x4.4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) - 2. Standard Pinout (Top View)
True package pinout (72 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) - 4. Package Dimensions (D×E×A)
WLCSP-72(3.8x4.4) · 4.40×3.80mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (72 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (32 figures · Page 1/3)
Showing 1–12 of 32 uncropped original figures for STM32L476
P65 · p65_fig01EXACT PACKAGE
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — Figure 12. STM32L476Mx WLCSP81 ballout(1) 1 2 3 4 5 6 7 8 VDDUSB PA15 PD2 PG9 PG14 PB3 PB7 VSS VSS PA14 PC12 PG10 PG13 VDDIO2 PB6 PC13
Figure 12. STM32L476Mx WLCSP81 ballout(1) 1 2 3 4 5 6 7 8 VDDUSB PA15 PD2 PG9 PG14 PB3 PB7 VSS VSS PA14 PC12 PG10 PG13 VDDIO2 PB6 PC13
P65 · p65_fig02EXACT PACKAGE
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — G
G
P66 · p66_fig01EXACT PACKAGE
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — Figure 14. STM32L476Jx, external SMPS device, WLCSP72 ballout(1)
Figure 14. STM32L476Jx, external SMPS device, WLCSP72 ballout(1)
P252 · p252_fig01EXACT PACKAGE
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — Figure 69. WLCSP - 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level
Figure 69. WLCSP - 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level
P253 · p253_fig01EXACT PACKAGE
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — Figure 70. WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale
Figure 70. WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale
P256 · p256_fig01EXACT PACKAGE
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — Figure 73. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level
Figure 73. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level
P1 · p01_fig01881×411px
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — • RTC with HW calendar, alarms and calibration
• RTC with HW calendar, alarms and calibration
P65 · p65_fig01P65
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — Datasheet Page 65 (p65_fig01)
Datasheet Page 65 (p65_fig01)
P66 · p66_fig01P66
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — Datasheet Page 66 (p66_fig01)
Datasheet Page 66 (p66_fig01)
P113 · p113_fig011751×2204px
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — Figure 20. Power supply scheme
Figure 20. Power supply scheme
P113 · p113_fig01P113
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — Datasheet Page 113 (p113_fig01)
Datasheet Page 113 (p113_fig01)
P156 · p156_fig011546×702px
STM32L476JEY6TR (WLCSP-72(3.8x4.4)) — Figure 25. Typical application with an 8 MHz crystal
Figure 25. Typical application with an 8 MHz crystal
Page 1 / 3 (32 extracted figures)

Technical Specifications & Part Details (STM32L476JEY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L476JEY6TR (WLCSP-72(3.8x4.4)) is a 72-pin embedded microcontroller unit (mcu) featuring a 3.80 × 4.40 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
80 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
18 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.80 × 4.40 × 0.56 mm (A1=0.17 mm)
Package family: WLCSP (WLCSP-72(3.8x4.4))
Pin Count & Lead PitchN / e
72 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol72 auto-grouped pins
OK
IPC-7351B Land Pattern72 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32L476 (14)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (WLCSP-72(3.8x4.4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.80 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
72P / 72Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-72(3.8x4.4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L476JEY6TR (WLCSP-72(3.8x4.4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L476JEY6TR (WLCSP-72(3.8x4.4))?

Manufactured by ST, the STM32L476JEY6TR is housed in a WLCSP-72(3.8x4.4) package with 72 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (VDDUSB: Power Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))), A2 (PA15: Multiplexed I/O & Peripheral Pin PA15 (General)), A3 (PD2: Multiplexed I/O & Peripheral Pin PD2 (General)), A4 (PG9: Multiplexed I/O & Peripheral Pin PG9 (General)), A5 (PG14: Multiplexed I/O & Peripheral Pin PG14 (General)), A6 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32L476JEY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L476JEY6TR (WLCSP-72(3.8x4.4)) has a nominal body envelope of 4.40 × 3.80 mm, pitch e = 0.40 mm, and 72 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L476JEY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L476JEY6TR (ST, WLCSP-72(3.8x4.4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (72 pins) & STM32L476 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A2PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
A3PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
A4PG9Digital_IOSignal terminal PG9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG9. Supported peripheral buses: General.
A5PG14Digital_IOSignal terminal PG14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG14. Supported peripheral buses: General.
A6PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
A7PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
A8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B2PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
B3PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
B4PG10Digital_IOSignal terminal PG10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG10. Supported peripheral buses: General.
B5PG13Digital_IOSignal terminal PG13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG13. Supported peripheral buses: General.
B6VDDIO2Power_InPrimary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B7PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
B8PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
B9VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C1PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
C2PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
C3PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
C4PG11Digital_IOSignal terminal PG11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG11. Supported peripheral buses: General.
C5PG12Digital_IOSignal terminal PG12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG12. Supported peripheral buses: General.
C6PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
C7PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
C8IOC8Digital_IOGeneral Purpose Digital I/O Pin IOC8
C9PC14 - OSC32_ IN(PC14)Digital_IOSignal terminal PC14 - OSC32_ IN(PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_ IN(PC14). Supported peripheral buses: RTC/CLK.
D1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
D2PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
D3PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
D7BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
D8PH1 - OSC_ OUT (PH1)Digital_IOSignal terminal PH1 - OSC_ OUT (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_ OUT (PH1). Supported peripheral buses: RTC/CLK.
D9PH0 - OSC_IN (PH0)Digital_IOSignal terminal PH0 - OSC_IN (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_IN (PH0). Supported peripheral buses: RTC/CLK.
E1PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E2PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
E3PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
E7PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
E8PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
E9NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F1PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
F2PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F3PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
F7PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC.
F8PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
F9PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
G1PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
G2PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
G3PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
G4PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
G5PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSSPI3NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
G6PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
G7PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSILCDVLCD. Supported peripheral buses: SPI, I2C, ADC.
G8VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
G9VSSA/ VREF -GND0V electrical ground return terminal (VSSA/ VREF -) for internal core logic, I/O drivers, and analog sub-blocks.
H1PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
H2PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
H3PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
H4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: ADC, PWM.
H5PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: UART, ADC.
H6PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: ADC, DAC, PWM.
H7PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
H8PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
H9VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
J1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
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