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C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6) — Symbol, Footprint IPC-7351B & 3D STEP Model

C43650215

SemiconductorWLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6 · 101 Pins · Pitch 0.35mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6)A2VDD50USBA4PM5A6PM12A8VDDA10VCAP4B1VDDB3VDD33USBB5PM6B7PM11B9VSSB11PC14-OSC32_IC2VSSC4VSSUSBC6PM9C8PD7C10VDDLDOD1VCAP3D3PM0D5DVDDD7PM13D9PB5D11PC15-OSC32_OE2VDDLDOE4PM1E6PM8E8PB3(JTDO/TRAE10VSSF1PA15(JTDI)F3PC10F5PM3F7BOOT0F9PB6F11VDDG2PA14(JTCK/SWG4PC11G6PM14G8PB7G10PC13H1PA10H3PA13(JTMS/SWH5PM2H7PB4(NJTRST)H9VBATH11VSSSMPSJ2PA9J4PA12J6PA5J8PB8J10VLXSMPSK1PA8K3PA11W10VDDW8VCAP1V11PA2V9VSSV7VDDXSPI1V5PP3V3PO2V1VDDXSPI1U10VREFPU8VDDLDOU6PP4U4VDDXSPI1U2PP1T11VDDAT9PA7T7VSST5PO5T3PP6T1VSSR10VSSAR8PB0R6PP2R4VSSR2PP7P11PH1-OSC_OUTP9PA0P7PO1P5PO4P3PP0P1VDDN10VREFMN8PA4N6PB2N4PP5N2PO0M11PH0-OSC_INM9PC0M7PA6M5PD12M3PB10M1PB15L10VFBSMPSL8PC1L6PB1L4PB12L2PB14K11VDDSMPSK9NRSTK7PA1K5PB11Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.271.166.061.055.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9-61.0-66.0-71.1mm
2. 2D FOOTPRINT
A2A4A6A8A10B1B3B5B7B9B11C2C4C6C8C10D1D3D5D7D9D11E2E4E6E8E10F1F3F5F7F9F11G2G4G6G8G10H1H3H5H7H9H11J2J4J6J8J10K1K3K5K7K9K11L2L4L6L8L10M1M3M5M7M9M11N2N4N6N8N10P1P3P5P7P9P11R2R4R6R8R10T1T3T5T7T9T11U2U4U6U8U10V1V3V5V7V9V11W8W10E=3.90mm · Pitch e=0.35mmD=3.80mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.90mm × 3.80mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (101/101)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A2VDD50USBPowerPower Supply Input (VDD50USB — 3.3V / 5.0V Standard Logic)
A4PM5I/OMultiplexed I/O & Peripheral Pin PM5 (General)
A6PM12I/OMultiplexed I/O & Peripheral Pin PM12 (General)
A8VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
A10VCAP4I/OMultiplexed I/O & Peripheral Pin VCAP4 (General)
B1VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
B3VDD33USBPowerPower Supply Input (VDD33USB — 3.3V / 5.0V Standard Logic)
B5PM6I/OMultiplexed I/O & Peripheral Pin PM6 (General)
B7PM11I/OMultiplexed I/O & Peripheral Pin PM11 (General)
B9VSSGNDGround Reference Pin (VSS)
B11PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
C2VSSGNDGround Reference Pin (VSS)
C4VSSUSBGNDGround Reference Pin (VSSUSB)
C6PM9I/OMultiplexed I/O & Peripheral Pin PM9 (General)
C8PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
C10VDDLDOPowerPower Supply Input (VDDLDO — 3.3V / 5.0V Standard Logic)
D1VCAP3I/OMultiplexed I/O & Peripheral Pin VCAP3 (General)
D3PM0I/OMultiplexed I/O & Peripheral Pin PM0 (General)
D5DVDDPowerPower Supply Input (DVDD — 3.3V / 5.0V Standard Logic)
D7PM13I/OMultiplexed I/O & Peripheral Pin PM13 (General)
D9PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
D11PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
E2VDDLDOPowerPower Supply Input (VDDLDO — 3.3V / 5.0V Standard Logic)
E4PM1I/OMultiplexed I/O & Peripheral Pin PM1 (General)
E6PM8I/OMultiplexed I/O & Peripheral Pin PM8 (General)
E8PB3(JTDO/TRACESWO)I/OMultiplexed I/O & Peripheral Pin PB3(JTDO/TRACESWO) (SWD/JTAG)
E10VSSGNDGround Reference Pin (VSS)
F1PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (SWD/JTAG)
F3PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
F5PM3I/OMultiplexed I/O & Peripheral Pin PM3 (General)
F7BOOT0IInput-Only Pin BOOT0 (General)
F9PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
F11VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
G2PA14(JTCK/SWK)I/OMultiplexed I/O & Peripheral Pin PA14(JTCK/SWK) (SWD/JTAG)
G4PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
G6PM14I/OMultiplexed I/O & Peripheral Pin PM14 (General)
G8PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
G10PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
H1PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
H3PA13(JTMS/SWD)I/OMultiplexed I/O & Peripheral Pin PA13(JTMS/SWD) (SWD/JTAG)
H5PM2I/OMultiplexed I/O & Peripheral Pin PM2 (General)
H7PB4(NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4(NJTRST) (SWD/JTAG)
H9VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
H11VSSSMPSGNDGround Reference Pin (VSSSMPS)
J2PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
J4PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
J6PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
J8PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
J10VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
K1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
K3PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
K5PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
K7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
K9NRSTISystem Enable & Hardware Reset (NRST)
K11VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V / 5.0V Standard Logic)
L2PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
L4PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
L6PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
L8PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
L10VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
M1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
M3PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
M5PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
M7PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
M9PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
M11PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
N2PO0I/OMultiplexed I/O & Peripheral Pin PO0 (General)
N4PP5I/OMultiplexed I/O & Peripheral Pin PP5 (General)
N6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
N8PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
N10VREFMI/OMultiplexed I/O & Peripheral Pin VREFM (General)
P1VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
P3PP0I/OMultiplexed I/O & Peripheral Pin PP0 (General)
P5PO4I/OMultiplexed I/O & Peripheral Pin PO4 (General)
P7PO1I/OMultiplexed I/O & Peripheral Pin PO1 (General)
P9PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
P11PH1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)
R2PP7I/OMultiplexed I/O & Peripheral Pin PP7 (General)
R4VSSGNDGround Reference Pin (VSS)
R6PP2I/OMultiplexed I/O & Peripheral Pin PP2 (General)
R8PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
R10VSSAGNDGround Reference Pin (VSSA)
T1VSSGNDGround Reference Pin (VSS)
T3PP6I/OMultiplexed I/O & Peripheral Pin PP6 (General)
T5PO5I/OMultiplexed I/O & Peripheral Pin PO5 (General)
T7VSSGNDGround Reference Pin (VSS)
T9PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
T11VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
U2PP1I/OMultiplexed I/O & Peripheral Pin PP1 (General)
U4VDDXSPI1PowerPower Supply Input (VDDXSPI1 — 3.3V / 5.0V Standard Logic)
U6PP4I/OMultiplexed I/O & Peripheral Pin PP4 (General)
U8VDDLDOPowerPower Supply Input (VDDLDO — 3.3V / 5.0V Standard Logic)
U10VREFPI/OMultiplexed I/O & Peripheral Pin VREFP (General)
V1VDDXSPI1PowerPower Supply Input (VDDXSPI1 — 3.3V / 5.0V Standard Logic)
V3PO2I/OMultiplexed I/O & Peripheral Pin PO2 (General)
V5PP3I/OMultiplexed I/O & Peripheral Pin PP3 (General)
V7VDDXSPI1PowerPower Supply Input (VDDXSPI1 — 3.3V / 5.0V Standard Logic)
V9VSSGNDGround Reference Pin (VSS)
V11PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
W8VCAP1I/OMultiplexed I/O & Peripheral Pin VCAP1 (General)
W10VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
PIN A2 VDD50USB
Power
Power Supply Input (VDD50USB — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDD50USB) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C43650215 (Semiconductor · WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6) - 2. Standard Pinout (Top View)
True package pinout (101 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6) - 4. Package Dimensions (D×E×A)
WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6 · 3.90×3.80mm · Pitch 0.35mmExpand ›
5. Recommended Land PatternLAND PATTERN
C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6) - 5. Recommended Land Pattern
IPC-7351B Footprint (101 Pads)Expand ›
6. Application SchematicSCHEMATIC
C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C43650215)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6) is a 101-pin standard electronic & interconnect component featuring a 3.80 × 3.90 × 0.55 mm mechanical envelope (lead pitch e = 0.35 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.80 × 3.90 × 0.55 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6)
Pin Count & Lead PitchN / e
101 Pins | Pitch e = 0.35 mm (13.8 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol101 auto-grouped pins
OK
IPC-7351B Land Pattern101 pads · Pitch 0.35mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.80 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.35mm
Pad Size (W × L)Level B
0.16 × 0.16 mm
Pins / Total PadsTopology
101P / 101Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6)?

Manufactured by Semiconductor, the C43650215 is housed in a WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6 package with 101 pins and a 0.35 mm lead pitch. Key pins include: A2 (VDD50USB: Power Supply Input (VDD50USB — 3.3V / 5.0V Standard Logic)), A4 (PM5: Multiplexed I/O & Peripheral Pin PM5 (General)), A6 (PM12: Multiplexed I/O & Peripheral Pin PM12 (General)), A8 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), A10 (VCAP4: Multiplexed I/O & Peripheral Pin VCAP4 (General)), B1 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for C43650215?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C43650215 (WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6) has a nominal body envelope of 3.90 × 3.80 mm, pitch e = 0.35 mm, and 101 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C43650215?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C43650215 (Semiconductor, WLCSP-101_L3.9-W3.8-P0.35_STM32H7R3V8Y6) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (101 pins) & STM32H7R3V8Y Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A2VDD50USBPower_InPrimary positive power supply input (VDD50USB) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
A4PM5Digital_IOSignal terminal PM5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM5. Supported peripheral buses: General.
A6PM12Digital_IOSignal terminal PM12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM12. Supported peripheral buses: General.
A8VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
A10VCAP4Digital_IOSignal terminal VCAP4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCAP4. Supported peripheral buses: General.
B1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B3VDD33USBPower_InPrimary positive power supply input (VDD33USB) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B5PM6Digital_IOSignal terminal PM6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM6. Supported peripheral buses: General.
B7PM11Digital_IOSignal terminal PM11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM11. Supported peripheral buses: General.
B9VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B11PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
C2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C4VSSUSBGND0V electrical ground return terminal (VSSUSB) for internal core logic, I/O drivers, and analog sub-blocks.
C6PM9Digital_IOSignal terminal PM9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM9. Supported peripheral buses: General.
C8PD7Digital_IOSignal terminal PD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
C10VDDLDOPower_InPrimary positive power supply input (VDDLDO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D1VCAP3Digital_IOSignal terminal VCAP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCAP3. Supported peripheral buses: General.
D3PM0Digital_IOSignal terminal PM0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM0. Supported peripheral buses: General.
D5DVDDPower_InPrimary positive power supply input (DVDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D7PM13Digital_IOSignal terminal PM13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM13. Supported peripheral buses: General.
D9PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
D11PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
E2VDDLDOPower_InPrimary positive power supply input (VDDLDO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E4PM1Digital_IOSignal terminal PM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM1. Supported peripheral buses: General.
E6PM8Digital_IOSignal terminal PM8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM8. Supported peripheral buses: General.
E8PB3(JTDO/TRACESWO)Digital_IOSignal terminal PB3(JTDO/TRACESWO) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3(JTDO/TRACESWO). Supported peripheral buses: SWD/JTAG.
E10VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F1PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15(JTDI). Supported peripheral buses: SWD/JTAG.
F3PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
F5PM3Digital_IOSignal terminal PM3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM3. Supported peripheral buses: General.
F7BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
F9PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
F11VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
G2PA14(JTCK/SWK)Digital_IOSignal terminal PA14(JTCK/SWK) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14(JTCK/SWK). Supported peripheral buses: SWD/JTAG.
G4PC11Digital_IOSignal terminal PC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
G6PM14Digital_IOSignal terminal PM14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM14. Supported peripheral buses: General.
G8PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
G10PC13Digital_IOSignal terminal PC13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
H1PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
H3PA13(JTMS/SWD)Digital_IOSignal terminal PA13(JTMS/SWD) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13(JTMS/SWD). Supported peripheral buses: SWD/JTAG.
H5PM2Digital_IOSignal terminal PM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PM2. Supported peripheral buses: General.
H7PB4(NJTRST)Digital_IOSignal terminal PB4(NJTRST) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4(NJTRST). Supported peripheral buses: SWD/JTAG.
H9VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
H11VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
J2PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
J4PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
J6PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
J8PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
J10VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
K1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
K3PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
K5PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
K7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
K9NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
K11VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
L2PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
L4PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
L6PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
L8PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
L10VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
M1PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
M3PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
M5PD12Digital_IOSignal terminal PD12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
M7PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
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