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STM32N657A0H3Q (VFBGA-169(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32N657A0H3Q

STVFBGA-169(6x6) · 169 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32N657A0H3Q (VFBGA-169(6x6))A1PDR_ONA2-A3OTG2_HSDMA4-A5OTG1_HSDMA6PC6A7PH1OSC OUT(PA8PC11A9PE11A10PE13A11PD7A12PD1A13VSSB1IOB1B2OTG2_IDB3OTG2_HSDPB4OTG1_IDB5OTG1_HSDPB6UCPD1_CC1B7PH0OSC IN(PHB8PC12B9PE14B10PE12B11PD10B12PD0B13PD15C1IOC1C2VBATC3OTG2_TXRTUNEC4VDDA18USBC5VDD33USBC6UCPD1_CC2C7PC9C8PH2C9PE5C10PD2C11PE7C12PD3C13PD14D1V08CAPD2PC13D3BOOT0D4PWR_OND5VDDA18AOND6PC10D7PC8D8VDDIO4D9PE15D10PD6D11PD12D12PE8D13PD4E1VDDA18PMUE2VSSAPMUE3VFBSMPSE4NRSTE5VSSAONE6VSSE7VDDCOREE8VSSE9VDDE10PB3E11PP1E12PP0E13PP3F1VSSSMPSF2VSSSMPSF3VSSSMPSF4VSSSMPSF5VSSF6VDDCOREF7VSSF8VDDCOREF9VSSF10PE2F11PP2F12PE0F13PP5G1VLXSMPSG2VLXSMPSG3VLXSMPSG4VLXSMPSG5VDDCOREG6VSSG7VDDCOREN13VSSN12PA3N11PA15(JTDI)N10PG2N9PG10N8PA6N7PA10N6PA14(JTCK/SWN5CSI_REXTN4CSI_D0PN3CSI_CKPN2CSI_D1PN1VSSM13PP13M12PN12M11PB4 (NJTRST)M10PB10M9PA0M8PA5M7PA9M6PA13(JTMS/SWM5VDDA18CSIM4CSI_D0NM3CSI_CKNM2CSI_D1NM1VREF+L13PN5L12PN4L11PB5 (JTDO/TRL10PB11L9PA1L8PA8L7PA11L6VDDCSIL5VDDA18ADCL4PF13L3PF12L2PF11L1PF8K13PN9K12PO3K11PP11K10PB12K9PG13K8PA2K7PA12K6PG14K5VSSAK4PF7K3PF15K2PF14K1PF2J13PP8J12PP9J11PP12J10VDDIO3J9VDDJ8VSSJ7VDDCOREJ6VSSJ5VDDA18PLLJ4PF3J3PF5J2PF10J1PF4H13PO5H12PO4H11PP10H10VDDIO3H9VSSH8VDDCOREH7VSSH6VDDCOREH5VSSH4VDDSMPSH3VDDSMPSH2VDDSMPSH1VDDSMPSG13PP6G12PP4G11PP7G10PB7G9VDDG8VSSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.8114.3109.2104.199.194.088.983.878.773.768.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6-73.7-78.7-83.8-88.9-94.0-99.1-104.1-109.2-114.3mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1L1M1N1A2B2C2D2E2F2G2H2J2K2L2M2N2A3B3C3D3E3F3G3H3J3K3L3M3N3A4B4C4D4E4F4G4H4J4K4L4M4N4A5B5C5D5E5F5G5H5J5K5L5M5N5A6B6C6D6E6F6G6H6J6K6L6M6N6A7B7C7D7E7F7G7H7J7K7L7M7N7A8B8C8D8E8F8G8H8J8K8L8M8N8A9B9C9D9E9F9G9H9J9K9L9M9N9A10B10C10D10E10F10G10H10J10K10L10M10N10A11B11C11D11E11F11G11H11J11K11L11M11N11A12B12C12D12E12F12G12H12J12K12L12M12N12A13B13C13D13E13F13G13H13J13K13L13M13N13E=6.00mm · Pitch e=0.40mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (169/169)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
A2-I/OMultiplexed I/O & Peripheral Pin - (General)
A3OTG2_HSDMI/OMultiplexed I/O & Peripheral Pin OTG2_HSDM (General)
A4-I/OMultiplexed I/O & Peripheral Pin - (General)
A5OTG1_HSDMI/OMultiplexed I/O & Peripheral Pin OTG1_HSDM (General)
A6PC6I/OMultiplexed I/O & Peripheral Pin PC6 (UART, PWM)
A7PH1OSC OUT(PH1) -_I/OMultiplexed I/O & Peripheral Pin PH1OSC OUT(PH1) -_ (RTC/CLK)
A8PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI, I2C)
A9PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
A10PE13I/OMultiplexed I/O & Peripheral Pin PE13 (I2C)
A11PD7I/OMultiplexed I/O & Peripheral Pin PD7 (SPI)
A12PD1I/OMultiplexed I/O & Peripheral Pin PD1 (UART)
A13VSSGNDGround Reference Pin (VSS)
B1IOB1I/OGeneral Purpose Digital I/O Pin IOB1
B2OTG2_IDI/OMultiplexed I/O & Peripheral Pin OTG2_ID (General)
B3OTG2_HSDPI/OMultiplexed I/O & Peripheral Pin OTG2_HSDP (General)
B4OTG1_IDI/OMultiplexed I/O & Peripheral Pin OTG1_ID (General)
B5OTG1_HSDPI/OMultiplexed I/O & Peripheral Pin OTG1_HSDP (General)
B6UCPD1_CC1I/OMultiplexed I/O & Peripheral Pin UCPD1_CC1 (General)
B7PH0OSC IN(PH0) -_I/OMultiplexed I/O & Peripheral Pin PH0OSC IN(PH0) -_ (RTC/CLK)
B8PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
B9PE14I/OMultiplexed I/O & Peripheral Pin PE14 (SPI, I2C)
B10PE12I/OMultiplexed I/O & Peripheral Pin PE12 (SPI)
B11PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
B12PD0I/OMultiplexed I/O & Peripheral Pin PD0 (UART)
B13PD15I/OMultiplexed I/O & Peripheral Pin PD15 (UART, I2C)
C1IOC1I/OGeneral Purpose Digital I/O Pin IOC1
C2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C3OTG2_TXRTUNEI/OMultiplexed I/O & Peripheral Pin OTG2_TXRTUNE (General)
C4VDDA18USBPowerPower Supply Input (VDDA18USB — 3.3V VDD (Max 4.0V))
C5VDD33USBPowerPower Supply Input (VDD33USB — 3.3V VDD (Max 4.0V))
C6UCPD1_CC2I/OMultiplexed I/O & Peripheral Pin UCPD1_CC2 (General)
C7PC9I/OMultiplexed I/O & Peripheral Pin PC9 (UART, I2C, RTC/CLK)
C8PH2I/OMultiplexed I/O & Peripheral Pin PH2 (UART)
C9PE5I/OMultiplexed I/O & Peripheral Pin PE5 (I2C, PWM)
C10PD2I/OMultiplexed I/O & Peripheral Pin PD2 (SPI)
C11PE7I/OMultiplexed I/O & Peripheral Pin PE7 (UART)
C12PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, I2C)
C13PD14I/OMultiplexed I/O & Peripheral Pin PD14 (UART, I2C)
D1V08CAPI/OMultiplexed I/O & Peripheral Pin V08CAP (General)
D2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
D3BOOT0IInput-Only Pin BOOT0 (General)
D4PWR_ONI/OMultiplexed I/O & Peripheral Pin PWR_ON (General)
D5VDDA18AONPowerPower Supply Input (VDDA18AON — 3.3V VDD (Max 4.0V))
D6PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI, I2C)
D7PC8I/OMultiplexed I/O & Peripheral Pin PC8 (UART, I2C)
D8VDDIO4PowerPower Supply Input (VDDIO4 — 3.3V VDD (Max 4.0V))
D9PE15I/OMultiplexed I/O & Peripheral Pin PE15 (UART, SPI)
D10PD6I/OMultiplexed I/O & Peripheral Pin PD6 (SPI)
D11PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
D12PE8I/OMultiplexed I/O & Peripheral Pin PE8 (UART)
D13PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART, I2C)
E1VDDA18PMUPowerPower Supply Input (VDDA18PMU — 3.3V VDD (Max 4.0V))
E2VSSAPMUGNDGround Reference Pin (VSSAPMU)
E3VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
E4NRSTISystem Enable & Hardware Reset (NRST)
E5VSSAONGNDGround Reference Pin (VSSAON)
E6VSSGNDGround Reference Pin (VSS)
E7VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
E8VSSGNDGround Reference Pin (VSS)
E9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E10PB3I/OMultiplexed I/O & Peripheral Pin PB3 (UART)
E11PP1I/OMultiplexed I/O & Peripheral Pin PP1 (General)
E12PP0I/OMultiplexed I/O & Peripheral Pin PP0 (General)
E13PP3I/OMultiplexed I/O & Peripheral Pin PP3 (General)
F1VSSSMPSGNDGround Reference Pin (VSSSMPS)
F2VSSSMPSGNDGround Reference Pin (VSSSMPS)
F3VSSSMPSGNDGround Reference Pin (VSSSMPS)
F4VSSSMPSGNDGround Reference Pin (VSSSMPS)
F5VSSGNDGround Reference Pin (VSS)
F6VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
F7VSSGNDGround Reference Pin (VSS)
F8VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
F9VSSGNDGround Reference Pin (VSS)
F10PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
F11PP2I/OMultiplexed I/O & Peripheral Pin PP2 (General)
F12PE0I/OMultiplexed I/O & Peripheral Pin PE0 (UART)
F13PP5I/OMultiplexed I/O & Peripheral Pin PP5 (General)
G1VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
G2VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
G3VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
G4VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
G5VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
G6VSSGNDGround Reference Pin (VSS)
G7VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
G8VSSGNDGround Reference Pin (VSS)
G9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G10PB7I/OMultiplexed I/O & Peripheral Pin PB7 (SPI)
G11PP7I/OMultiplexed I/O & Peripheral Pin PP7 (General)
G12PP4I/OMultiplexed I/O & Peripheral Pin PP4 (General)
G13PP6I/OMultiplexed I/O & Peripheral Pin PP6 (General)
H1VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
H2VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
H3VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
H4VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
H5VSSGNDGround Reference Pin (VSS)
H6VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
H7VSSGNDGround Reference Pin (VSS)
H8VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
H9VSSGNDGround Reference Pin (VSS)
H10VDDIO3PowerPower Supply Input (VDDIO3 — 3.3V VDD (Max 4.0V))
H11PP10I/OMultiplexed I/O & Peripheral Pin PP10 (General)
H12PO4I/OMultiplexed I/O & Peripheral Pin PO4 (General)
H13PO5I/OMultiplexed I/O & Peripheral Pin PO5 (General)
J1PF4I/OMultiplexed I/O & Peripheral Pin PF4 (SPI, ADC)
J2PF10I/OMultiplexed I/O & Peripheral Pin PF10 (General)
J3PF5I/OMultiplexed I/O & Peripheral Pin PF5 (UART, SPI)
J4PF3I/OMultiplexed I/O & Peripheral Pin PF3 (ADC)
J5VDDA18PLLPowerPower Supply Input (VDDA18PLL — 3.3V VDD (Max 4.0V))
J6VSSGNDGround Reference Pin (VSS)
J7VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
J8VSSGNDGround Reference Pin (VSS)
J9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J10VDDIO3PowerPower Supply Input (VDDIO3 — 3.3V VDD (Max 4.0V))
J11PP12I/OMultiplexed I/O & Peripheral Pin PP12 (General)
J12PP9I/OMultiplexed I/O & Peripheral Pin PP9 (SPI)
J13PP8I/OMultiplexed I/O & Peripheral Pin PP8 (SPI)
K1PF2I/OMultiplexed I/O & Peripheral Pin PF2 (UART, SPI)
K2PF14I/OMultiplexed I/O & Peripheral Pin PF14 (UART, ADC)
K3PF15I/OMultiplexed I/O & Peripheral Pin PF15 (UART)
K4PF7I/OMultiplexed I/O & Peripheral Pin PF7 (SPI, ADC, PWM)
K5VSSAGNDGround Reference Pin (VSSA)
K6PG14I/OMultiplexed I/O & Peripheral Pin PG14 (UART, SPI)
K7PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, SPI, ADC)
K8PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, SPI, ADC)
K9PG13I/OMultiplexed I/O & Peripheral Pin PG13 (UART, PWM)
K10PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI)
K11PP11I/OMultiplexed I/O & Peripheral Pin PP11 (General)
K12PO3I/OMultiplexed I/O & Peripheral Pin PO3 (General)
K13PN9I/OMultiplexed I/O & Peripheral Pin PN9 (General)
L1PF8I/OMultiplexed I/O & Peripheral Pin PF8 (UART)
L2PF11I/OMultiplexed I/O & Peripheral Pin PF11 (SPI, ADC)
L3PF12I/OMultiplexed I/O & Peripheral Pin PF12 (UART, ADC)
L4PF13I/OMultiplexed I/O & Peripheral Pin PF13 (UART, ADC)
L5VDDA18ADCPowerPower Supply Input (VDDA18ADC — 3.3V VDD (Max 4.0V))
L6VDDCSIPowerPower Supply Input (VDDCSI — 3.3V VDD (Max 4.0V))
L7PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, SPI, ADC)
L8PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, I2C, ADC, RTC/CLK)
L9PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
L10PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C, ADC)
L11PB5 (JTDO/TRACESWO)I/OMultiplexed I/O & Peripheral Pin PB5 (JTDO/TRACESWO) (SPI, SWD/JTAG)
L12PN4I/OMultiplexed I/O & Peripheral Pin PN4 (General)
L13PN5I/OMultiplexed I/O & Peripheral Pin PN5 (General)
M1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
M2CSI_D1NI/OMultiplexed I/O & Peripheral Pin CSI_D1N (General)
M3CSI_CKNI/OMultiplexed I/O & Peripheral Pin CSI_CKN (General)
M4CSI_D0NI/OMultiplexed I/O & Peripheral Pin CSI_D0N (General)
M5VDDA18CSIPowerPower Supply Input (VDDA18CSI — 3.3V VDD (Max 4.0V))
M6PA13(JTMS/SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13(JTMS/SWDIO) (SWD/JTAG)
M7PA9I/OMultiplexed I/O & Peripheral Pin PA9 (SPI, I2C, ADC)
M8PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, I2C, ADC)
M9PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM)
M10PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, I2C, ADC)
M11PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (UART, SPI, SWD/JTAG)
M12PN12I/OMultiplexed I/O & Peripheral Pin PN12 (General)
M13PP13I/OMultiplexed I/O & Peripheral Pin PP13 (General)
N1VSSGNDGround Reference Pin (VSS)
N2CSI_D1PI/OMultiplexed I/O & Peripheral Pin CSI_D1P (General)
N3CSI_CKPI/OMultiplexed I/O & Peripheral Pin CSI_CKP (General)
N4CSI_D0PI/OMultiplexed I/O & Peripheral Pin CSI_D0P (General)
N5CSI_REXTI/OMultiplexed I/O & Peripheral Pin CSI_REXT (General)
N6PA14(JTCK/SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14(JTCK/SWCLK) (SWD/JTAG)
N7PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, ADC, PWM)
N8PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, I2C, ADC)
N9PG10I/OMultiplexed I/O & Peripheral Pin PG10 (UART, SPI)
N10PG2I/OMultiplexed I/O & Peripheral Pin PG2 (UART, SPI)
N11PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)
N12PA3I/OMultiplexed I/O & Peripheral Pin PA3 (SPI)
N13VSSGNDGround Reference Pin (VSS)
PIN A1 PDR_ON
I/O
Multiplexed I/O & Peripheral Pin PDR_ON (General)
Design note: Signal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32N657A0H3Q (ST · VFBGA-169(6x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32N657A0H3Q (VFBGA-169(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32N657A0H3Q (VFBGA-169(6x6)) - 2. Standard Pinout (Top View)
True package pinout (169 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32N657A0H3Q (VFBGA-169(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32N657A0H3Q (VFBGA-169(6x6)) - 4. Package Dimensions (D×E×A)
VFBGA-169(6x6) · 6.00×6.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32N657A0H3Q (VFBGA-169(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (169 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32N657A0H3Q (VFBGA-169(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for STM32N657
P84 · p84_fig01EXACT PACKAGE
STM32N657A0H3Q (VFBGA-169(6x6)) — Figure 8. VFBGA169 ballout
Figure 8. VFBGA169 ballout
P241 · p241_fig01EXACT PACKAGE
STM32N657A0H3Q (VFBGA-169(6x6)) — Figure 68. VFBGA169 - Outline(13)
Figure 68. VFBGA169 - Outline(13)
P26 · p26_fig011751×848px
STM32N657A0H3Q (VFBGA-169(6x6)) — Figure 2. SMPS configurations
Figure 2. SMPS configurations
P83 · p83_fig011752×1837px
STM32N657A0H3Q (VFBGA-169(6x6)) — Figure 7. VFBGA142 ballout
Figure 7. VFBGA142 ballout
P138 · p138_fig011764×2345px
STM32N657A0H3Q (VFBGA-169(6x6)) — Figure 16. Power supply scheme VDDIO4
Figure 16. Power supply scheme VDDIO4
P163 · p163_fig011546×467px
STM32N657A0H3Q (VFBGA-169(6x6)) — Figure 21. Typical application with a 40 MHz crystal fHSE CL1 RF 40 MHz crystal
Figure 21. Typical application with a 40 MHz crystal fHSE CL1 RF 40 MHz crystal
P163 · p163_fig021875×852px
STM32N657A0H3Q (VFBGA-169(6x6)) — Figure 22. LSE clock source AC timing diagram (digital bypass)
Figure 22. LSE clock source AC timing diagram (digital bypass)
P204 · p204_fig011546×981px
STM32N657A0H3Q (VFBGA-169(6x6)) — Figure 45. ADC accuracy characteristics
Figure 45. ADC accuracy characteristics
P204 · p204_fig021546×750px
STM32N657A0H3Q (VFBGA-169(6x6)) — Figure 46. Typical connection diagram using the ADC with TT pins featuring analog switch function
Figure 46. Typical connection diagram using the ADC with TT pins featuring analog switch function
P255 · p255_fig011752×1356px
STM32N657A0H3Q (VFBGA-169(6x6)) — Figure 74. VFBGA264 - Recommended footprint
Figure 74. VFBGA264 - Recommended footprint

Technical Specifications & Part Details (STM32N657A0H3Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32N657A0H3Q (VFBGA-169(6x6)) is a 169-pin embedded microcontroller unit (mcu) featuring a 6.00 × 6.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
800 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 0.85 mm (A1=0.22 mm)
Package family: BGA (VFBGA-169(6x6))
Pin Count & Lead PitchN / e
169 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PA6): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol169 auto-grouped pins
OK
IPC-7351B Land Pattern169 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VFBGA-169(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.21 × 0.21 mm
Pins / Total PadsTopology
169P / 169Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
VFBGA-169(6x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32N657A0H3Q (VFBGA-169(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32N657A0H3Q (VFBGA-169(6x6))?

Manufactured by ST, the STM32N657A0H3Q is housed in a VFBGA-169(6x6) package with 169 pins and a 0.40 mm lead pitch. Key pins include: A1 (PDR_ON: Multiplexed I/O & Peripheral Pin PDR_ON (General)), A2 (-: Multiplexed I/O & Peripheral Pin - (General)), A3 (OTG2_HSDM: Multiplexed I/O & Peripheral Pin OTG2_HSDM (General)), A4 (-: Multiplexed I/O & Peripheral Pin - (General)), A5 (OTG1_HSDM: Multiplexed I/O & Peripheral Pin OTG1_HSDM (General)), A6 (PC6: Multiplexed I/O & Peripheral Pin PC6 (UART, PWM)).

What are the IPC-7351B PCB Footprint dimensions for STM32N657A0H3Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32N657A0H3Q (VFBGA-169(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.40 mm, and 169 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32N657A0H3Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32N657A0H3Q (ST, VFBGA-169(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (169 pins) & STM32N657 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PDR_ONDigital_IOSignal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
A2-Digital_IOSignal terminal - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: -. Supported peripheral buses: General.
A3OTG2_HSDMDigital_IOSignal terminal OTG2_HSDM (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG2_HSDM. Supported peripheral buses: General.
A4-Digital_IOSignal terminal - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: -. Supported peripheral buses: General.
A5OTG1_HSDMDigital_IOSignal terminal OTG1_HSDM (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG1_HSDM. Supported peripheral buses: General.
A6PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: UART, PWM.
A7PH1OSC OUT(PH1) -_Digital_IOSignal terminal PH1OSC OUT(PH1) -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1OSC OUT(PH1) -_. Supported peripheral buses: RTC/CLK.
A8PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C4_SDA, SPI3_MISO. Supported peripheral buses: UART, SPI, I2C.
A9PE11Digital_IOSignal terminal PE11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: General.
A10PE13Digital_IOSignal terminal PE13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE13. Supported peripheral buses: I2C.
A11PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MOSI, SPI3_NSS. Supported peripheral buses: SPI.
A12PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: UART.
A13VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B1IOB1Digital_IOGeneral Purpose Digital I/O Pin IOB1
B2OTG2_IDDigital_IOSignal terminal OTG2_ID (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG2_ID. Supported peripheral buses: General.
B3OTG2_HSDPDigital_IOSignal terminal OTG2_HSDP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG2_HSDP. Supported peripheral buses: General.
B4OTG1_IDDigital_IOSignal terminal OTG1_ID (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG1_ID. Supported peripheral buses: General.
B5OTG1_HSDPDigital_IOSignal terminal OTG1_HSDP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG1_HSDP. Supported peripheral buses: General.
B6UCPD1_CC1Digital_IOSignal terminal UCPD1_CC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: UCPD1_CC1. Supported peripheral buses: General.
B7PH0OSC IN(PH0) -_Digital_IOSignal terminal PH0OSC IN(PH0) -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0OSC IN(PH0) -_. Supported peripheral buses: RTC/CLK.
B8PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI6_SCK, SPI3_MOSI. Supported peripheral buses: UART, SPI.
B9PE14Digital_IOSignal terminal PE14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C4_SDA, SPI4_MOSI_SAI2MCLKB. Supported peripheral buses: SPI, I2C.
B10PE12Digital_IOSignal terminal PE12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE12. Supported peripheral buses: SPI.
B11PD10Digital_IOSignal terminal PD10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
B12PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: UART.
B13PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, I2C.
C1IOC1Digital_IOGeneral Purpose Digital I/O Pin IOC1
C2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C3OTG2_TXRTUNEDigital_IOSignal terminal OTG2_TXRTUNE (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG2_TXRTUNE. Supported peripheral buses: General.
C4VDDA18USBPower_InPrimary positive power supply input (VDDA18USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C5VDD33USBPower_InPrimary positive power supply input (VDD33USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C6UCPD1_CC2Digital_IOSignal terminal UCPD1_CC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: UCPD1_CC2. Supported peripheral buses: General.
C7PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C3_SDA. Supported peripheral buses: UART, I2C, RTC/CLK.
C8PH2Digital_IOSignal terminal PH2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH2. Supported peripheral buses: UART.
C9PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C, PWM.
C10PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI.
C11PE7Digital_IOSignal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: UART.
C12PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SMBA. Supported peripheral buses: UART, I2C.
C13PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C.
D1V08CAPDigital_IOSignal terminal V08CAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: V08CAP. Supported peripheral buses: General.
D2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
D3BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
D4PWR_ONDigital_IOSignal terminal PWR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PWR_ON. Supported peripheral buses: General.
D5VDDA18AONPower_InPrimary positive power supply input (VDDA18AON) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D6PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI, I2C.
D7PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: UART, I2C.
D8VDDIO4Power_InPrimary positive power supply input (VDDIO4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D9PE15Digital_IOSignal terminal PE15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI5_SCK. Supported peripheral buses: UART, SPI.
D10PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI.
D11PD12Digital_IOSignal terminal PD12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
D12PE8Digital_IOSignal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: UART.
D13PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: UART, I2C.
E1VDDA18PMUPower_InPrimary positive power supply input (VDDA18PMU) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E2VSSAPMUGND0V electrical ground return terminal (VSSAPMU) for internal core logic, I/O drivers, and analog sub-blocks.
E3VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
E4NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E5VSSAONGND0V electrical ground return terminal (VSSAON) for internal core logic, I/O drivers, and analog sub-blocks.
E6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E7VDDCOREPower_InPrimary positive power supply input (VDDCORE) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E10PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: UART.
E11PP1Digital_IOSignal terminal PP1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP1. Supported peripheral buses: General.
E12PP0Digital_IOSignal terminal PP0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP0. Supported peripheral buses: General.
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