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CH592X (QFN-32-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH592X

WCHID: C42442063QFN-32-EP(4x4) · 33 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH592X (QFN-32-EP(4x4))1PA10/X32KI/T2PB6/RTS/PWM83PB0/PWM6/CTS4VDCID5VSW6VIO33/VDD337NC8IO09PA8/RXD1/AIN10PA9/TMR0/TXD11PB15/TCK/MIS12IO713PB13/SCK0_/T14PB12/SCS_/RX15PB11/UD+/TMR16PB10/UD-/TMR17PB7/TXD0/PWM33EP32PA11/X32KO/T31PA12/SCS/PWM30PA13/SCK0/PW29PA14/MOSI/TX28PA15/MISO/RX27PA5/TXD3/AIN26PA4/RXD3/AIN25VDCIA24ANT23VINTA22X32MI21X32MO20PB22/TMR3/RX19IO2018PB4/RXD0/PWMGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.227.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA10/X32KI/TMR1I/OMultiplexed I/O & Peripheral Pin PA10/X32KI/TMR1 (General)
2PB6/RTS/PWM8/AIN9I/OMultiplexed I/O & Peripheral Pin PB6/RTS/PWM8/AIN9 (UART, ADC, PWM)
3PB0/PWM6/CTS/AIN8I/OMultiplexed I/O & Peripheral Pin PB0/PWM6/CTS/AIN8 (UART, ADC, PWM)
4VDCIDI/OMultiplexed I/O & Peripheral Pin VDCID (General)
5VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
6VIO33/VDD33PowerPower Supply Input (VIO33/VDD33 — 3.3V / 5.0V Standard Logic)
7NCNCNo Connect (Leave Floating)
8IO0I/OGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9PA8/RXD1/AIN12I/OMultiplexed I/O & Peripheral Pin PA8/RXD1/AIN12 (UART, ADC)
10PA9/TMR0/TXD1/AIN13I/OMultiplexed I/O & Peripheral Pin PA9/TMR0/TXD1/AIN13 (UART, ADC)
11PB15/TCK/MISO_/SCL/DTRI/OMultiplexed I/O & Peripheral Pin PB15/TCK/MISO_/SCL/DTR (UART, SPI, I2C)
12IO7I/OGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13PB13/SCK0_/TXD1_/DCDI/OMultiplexed I/O & Peripheral Pin PB13/SCK0_/TXD1_/DCD (UART, SPI)
14PB12/SCS_/RXD1_/RII/OMultiplexed I/O & Peripheral Pin PB12/SCS_/RXD1_/RI (UART)
15PB11/UD+/TMR2I/OMultiplexed I/O & Peripheral Pin PB11/UD+/TMR2 (USB)
16PB10/UD-/TMR1I/OMultiplexed I/O & Peripheral Pin PB10/UD-/TMR1 (USB)
17PB7/TXD0/PWM9I/OMultiplexed I/O & Peripheral Pin PB7/TXD0/PWM9 (UART, PWM)
18PB4/RXD0/PWM7I/OMultiplexed I/O & Peripheral Pin PB4/RXD0/PWM7 (UART, PWM)
19IO20I/OGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20PB22/TMR3/RXD2I/OMultiplexed I/O & Peripheral Pin PB22/TMR3/RXD2 (UART)
21X32MOI/OMultiplexed I/O & Peripheral Pin X32MO (General)
22X32MII/OMultiplexed I/O & Peripheral Pin X32MI (General)
23VINTAPowerPower Supply Input (VINTA — 3.3V / 5.0V Standard Logic)
24ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
25VDCIAI/OMultiplexed I/O & Peripheral Pin VDCIA (General)
26PA4/RXD3/AIN0I/OMultiplexed I/O & Peripheral Pin PA4/RXD3/AIN0 (UART, ADC)
27PA5/TXD3/AIN1I/OMultiplexed I/O & Peripheral Pin PA5/TXD3/AIN1 (UART, ADC)
28PA15/MISO/RXD0_/AIN5I/OMultiplexed I/O & Peripheral Pin PA15/MISO/RXD0_/AIN5 (UART, SPI, ADC)
29PA14/MOSI/TXD0_/AIN4I/OMultiplexed I/O & Peripheral Pin PA14/MOSI/TXD0_/AIN4 (UART, SPI, ADC)
30PA13/SCK0/PWM5/AIN3I/OMultiplexed I/O & Peripheral Pin PA13/SCK0/PWM5/AIN3 (SPI, ADC, PWM)
31PA12/SCS/PWM4/AIN2I/OMultiplexed I/O & Peripheral Pin PA12/SCS/PWM4/AIN2 (ADC, PWM)
32PA11/X32KO/TMR2I/OMultiplexed I/O & Peripheral Pin PA11/X32KO/TMR2 (General)
33EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 PA10/X32KI/TMR1
I/O
Multiplexed I/O & Peripheral Pin PA10/X32KI/TMR1 (General)
Design note: Signal terminal PA10/X32KI/TMR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10/X32KI/TMR1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH592X (WCH · QFN-32-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH592X (QFN-32-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH592X (QFN-32-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH592X (QFN-32-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH592X (QFN-32-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-32-EP(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH592X (QFN-32-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH592X (QFN-32-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH591 / CH592
P1 · p01_fig01247×133px
CH592X (QFN-32-EP(4x4)) — 概述
概述
P3 · p03_fig011716×1996px
CH592X (QFN-32-EP(4x4)) — PA14/MOSI/TXD0_/AIN4 18 | PA13/SCK0/PWM5/AIN3 19 | PA15/MISO/RXD0_/AIN5 17 | 13 14 | 11 | 2 | 5 | 0 | 15 | 12 | 1 | PA12/SCS/PWM4/AIN2 20 | 4 3 | VDCIA 16 | CH592D | PB11/UD+/TMR2_ PB12/SCS_/RXD1_ | PB15/TCK/MISO_/SCL PB14/TIO/MOSI_/SDA/PWM
PA14/MOSI/TXD0_/AIN4 18 | PA13/SCK0/PWM5/AIN3 19 | PA15/MISO/RXD0_/AIN5 17 | 13 14 | 11 | 2 | 5 | 0 | 15 | 12 | 1 | PA12/SCS/PWM4/AIN2 20 | 4 3 | VDCIA 16 | CH592D | PB11/UD+/TMR2_ PB12/SCS_/RXD1_ | PB15/TCK/MISO_/SCL PB14/TIO/MOSI_/SDA/PWM
P7 · p07_fig011901×1755px
CH592X (QFN-32-EP(4x4)) — CH592/CH591 数据手册 https://wch.cn
CH592/CH591 数据手册 https://wch.cn
P93 · p93_fig011713×1837px
CH592X (QFN-32-EP(4x4)) — V1.8 91
V1.8 91
P120 · p120_fig011723×651px
CH592X (QFN-32-EP(4x4)) — CH592 1.3 1.5 1.7 V CH591 1.8 2.05 2.3 V
CH592 1.3 1.5 1.7 V CH591 1.8 2.05 2.3 V
P120 · p120_fig01P120
CH592X (QFN-32-EP(4x4)) — Datasheet Page 120 (p120_fig01)
Datasheet Page 120 (p120_fig01)

Technical Specifications & Part Details (CH592X)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH592X (QFN-32-EP(4x4)) is a 32-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, SPI, I2C, ADC, PWM, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-32-EP(4x4))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, SPI, I2C, ADC, PWM, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.80×2.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-32-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-32-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH592X (QFN-32-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH592X (QFN-32-EP(4x4))?

Manufactured by WCH, the CH592X is housed in a QFN-32-EP(4x4) package with 33 pins and a 0.40 mm lead pitch. Key pins include: 1 (PA10/X32KI/TMR1: Multiplexed I/O & Peripheral Pin PA10/X32KI/TMR1 (General)), 2 (PB6/RTS/PWM8/AIN9: Multiplexed I/O & Peripheral Pin PB6/RTS/PWM8/AIN9 (UART, ADC, PWM)), 3 (PB0/PWM6/CTS/AIN8: Multiplexed I/O & Peripheral Pin PB0/PWM6/CTS/AIN8 (UART, ADC, PWM)), 4 (VDCID: Multiplexed I/O & Peripheral Pin VDCID (General)), 5 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 6 (VIO33/VDD33: Power Supply Input (VIO33/VDD33 — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for CH592X?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH592X (QFN-32-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 2.80 × 2.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH592X?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH592X (WCH, QFN-32-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & CH591 / CH592 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA10/X32KI/TMR1Digital_IOSignal terminal PA10/X32KI/TMR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10/X32KI/TMR1. Supported peripheral buses: General.
2PB6/RTS/PWM8/AIN9AnalogSignal terminal PB6/RTS/PWM8/AIN9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6/RTS/PWM8/AIN9. Supported peripheral buses: UART, ADC, PWM.
3PB0/PWM6/CTS/AIN8AnalogSignal terminal PB0/PWM6/CTS/AIN8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/PWM6/CTS/AIN8. Supported peripheral buses: UART, ADC, PWM.
4VDCIDDigital_IOSignal terminal VDCID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCID. Supported peripheral buses: General.
5VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
6VIO33/VDD33Power_InPrimary positive power supply input (VIO33/VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7NCNo_ConnectNo Connect (Leave Floating)
8IO0Digital_IOGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9PA8/RXD1/AIN12Digital_IOSignal terminal PA8/RXD1/AIN12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8/RXD1/AIN12. Supported peripheral buses: UART, ADC.
10PA9/TMR0/TXD1/AIN13Digital_IOSignal terminal PA9/TMR0/TXD1/AIN13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9/TMR0/TXD1/AIN13. Supported peripheral buses: UART, ADC.
11PB15/TCK/MISO_/SCL/DTRDigital_IOSignal terminal PB15/TCK/MISO_/SCL/DTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15/TCK/MISO_/SCL/DTR. Supported peripheral buses: UART, SPI, I2C.
12IO7Digital_IOGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13PB13/SCK0_/TXD1_/DCDDigital_IOSignal terminal PB13/SCK0_/TXD1_/DCD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13/SCK0_/TXD1_/DCD. Supported peripheral buses: UART, SPI.
14PB12/SCS_/RXD1_/RIDigital_IOSignal terminal PB12/SCS_/RXD1_/RI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12/SCS_/RXD1_/RI. Supported peripheral buses: UART.
15PB11/UD+/TMR2Digital_IOSignal terminal PB11/UD+/TMR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11/UD+/TMR2. Supported peripheral buses: USB.
16PB10/UD-/TMR1Digital_IOSignal terminal PB10/UD-/TMR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10/UD-/TMR1. Supported peripheral buses: USB.
17PB7/TXD0/PWM9Digital_IOSignal terminal PB7/TXD0/PWM9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/TXD0/PWM9. Supported peripheral buses: UART, PWM.
18PB4/RXD0/PWM7Digital_IOSignal terminal PB4/RXD0/PWM7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4/RXD0/PWM7. Supported peripheral buses: UART, PWM.
19IO20Digital_IOGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20PB22/TMR3/RXD2Digital_IOSignal terminal PB22/TMR3/RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB22/TMR3/RXD2. Supported peripheral buses: UART.
21X32MODigital_IOSignal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General.
22X32MIDigital_IOSignal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General.
23VINTAPower_InPrimary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
25VDCIADigital_IOSignal terminal VDCIA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCIA. Supported peripheral buses: General.
26PA4/RXD3/AIN0Digital_IOSignal terminal PA4/RXD3/AIN0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/RXD3/AIN0. Supported peripheral buses: UART, ADC.
27PA5/TXD3/AIN1Digital_IOSignal terminal PA5/TXD3/AIN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/TXD3/AIN1. Supported peripheral buses: UART, ADC.
28PA15/MISO/RXD0_/AIN5Digital_IOSignal terminal PA15/MISO/RXD0_/AIN5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15/MISO/RXD0_/AIN5. Supported peripheral buses: UART, SPI, ADC.
29PA14/MOSI/TXD0_/AIN4Digital_IOSignal terminal PA14/MOSI/TXD0_/AIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/MOSI/TXD0_/AIN4. Supported peripheral buses: UART, SPI, ADC.
30PA13/SCK0/PWM5/AIN3Digital_IOSignal terminal PA13/SCK0/PWM5/AIN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13/SCK0/PWM5/AIN3. Supported peripheral buses: SPI, ADC, PWM.
31PA12/SCS/PWM4/AIN2AnalogSignal terminal PA12/SCS/PWM4/AIN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/SCS/PWM4/AIN2. Supported peripheral buses: ADC, PWM.
32PA11/X32KO/TMR2Digital_IOSignal terminal PA11/X32KO/TMR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/X32KO/TMR2. Supported peripheral buses: General.
33EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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