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CH390L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH390L

WCHID: C42442061LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH390L (LQFP-48(7x7))1VDDK2RSVD.3MDIRP4MDIRN5GND6GND7MDITP8MDITN9RSVD.10D711D612D513D414D315GND16D217D118D019EEDIO20EECK21EECS/MD822D15/WOL23AVDD3324D1448GND47GND46NC45GND44XO43XI42AVDD3341GND40RSTB39LED1SPD38LED2ACT37CSB36WRB35RDB34INT33GND32CMD31D8/GPIO130VDDIO29D9/GPIO228D10/GPIO327D11/GPIO426D12/GPIO525D13/GPIO6Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDKPowerPower Supply Input (VDDK — 3.3V / 5.0V Standard Logic)
2RSVD.I/OMultiplexed I/O & Peripheral Pin RSVD. (General)
3MDIRPI/OMultiplexed I/O & Peripheral Pin MDIRP (General)
4MDIRNI/OMultiplexed I/O & Peripheral Pin MDIRN (General)
5GNDGNDGround Reference Pin (GND)
6GNDGNDGround Reference Pin (GND)
7MDITPI/OMultiplexed I/O & Peripheral Pin MDITP (General)
8MDITNI/OMultiplexed I/O & Peripheral Pin MDITN (General)
9RSVD.I/OMultiplexed I/O & Peripheral Pin RSVD. (General)
10D7I/OMultiplexed I/O & Peripheral Pin D7 (General)
11D6I/OMultiplexed I/O & Peripheral Pin D6 (General)
12D5I/OMultiplexed I/O & Peripheral Pin D5 (General)
13D4I/OMultiplexed I/O & Peripheral Pin D4 (General)
14D3I/OMultiplexed I/O & Peripheral Pin D3 (General)
15GNDGNDGround Reference Pin (GND)
16D2I/OMultiplexed I/O & Peripheral Pin D2 (General)
17D1I/OMultiplexed I/O & Peripheral Pin D1 (General)
18D0I/OMultiplexed I/O & Peripheral Pin D0 (General)
19EEDIOI/OMultiplexed I/O & Peripheral Pin EEDIO (General)
20EECKI/OMultiplexed I/O & Peripheral Pin EECK (General)
21EECS/MD8I/OMultiplexed I/O & Peripheral Pin EECS/MD8 (General)
22D15/WOLI/OMultiplexed I/O & Peripheral Pin D15/WOL (General)
23AVDD33PowerPower Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)
24D14I/OMultiplexed I/O & Peripheral Pin D14 (General)
25D13/GPIO6I/OMultiplexed I/O & Peripheral Pin D13/GPIO6 (General)
26D12/GPIO5I/OMultiplexed I/O & Peripheral Pin D12/GPIO5 (General)
27D11/GPIO4I/OMultiplexed I/O & Peripheral Pin D11/GPIO4 (General)
28D10/GPIO3I/OMultiplexed I/O & Peripheral Pin D10/GPIO3 (General)
29D9/GPIO2I/OMultiplexed I/O & Peripheral Pin D9/GPIO2 (General)
30VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
31D8/GPIO1I/OMultiplexed I/O & Peripheral Pin D8/GPIO1 (General)
32CMDI/OMultiplexed I/O & Peripheral Pin CMD (General)
33GNDGNDGround Reference Pin (GND)
34INTI/OMultiplexed I/O & Peripheral Pin INT (General)
35RDBI/OMultiplexed I/O & Peripheral Pin RDB (General)
36WRBI/OMultiplexed I/O & Peripheral Pin WRB (General)
37CSBI/OMultiplexed I/O & Peripheral Pin CSB (General)
38LED2ACTI/OMultiplexed I/O & Peripheral Pin LED2ACT (General)
39LED1SPDI/OMultiplexed I/O & Peripheral Pin LED1SPD (General)
40RSTBI/OMultiplexed I/O & Peripheral Pin RSTB (General)
41GNDGNDGround Reference Pin (GND)
42AVDD33PowerPower Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)
43XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
44XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
45GNDGNDGround Reference Pin (GND)
46NCI/OMultiplexed I/O & Peripheral Pin NC (General)
47GNDGNDGround Reference Pin (GND)
48GNDGNDGround Reference Pin (GND)
PIN 1 VDDK
Power
Power Supply Input (VDDK — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH390L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH390L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH390L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH390L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH390L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH390L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH390L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH390
P1 · p01_fig01248×133px
CH390L (LQFP-48(7x7)) — 1、概述
1、概述
P1 · p01_fig021739×1053px
CH390L (LQFP-48(7x7)) — 2、特点
2、特点
P2 · p02_fig011731×2095px
CH390L (LQFP-48(7x7)) — 2.建议优选小体积的CH390D 和CH390F。 3.CH390 分早期的VDDK 分立版和后期的VDDK 合并版，主要区别是：合并版在封装时将AVDDK 内 部短接到VDDK，合并版向前兼容分立版，批号倒数第6 位为0 或批号倒数第5 位为2 的CH390 是VDDK 分立版，否则是合并版。
2.建议优选小体积的CH390D 和CH390F。 3.CH390 分早期的VDDK 分立版和后期的VDDK 合并版，主要区别是：合并版在封装时将AVDDK 内 部短接到VDDK，合并版向前兼容分立版，批号倒数第6 位为0 或批号倒数第5 位为2 的CH390 是VDDK 分立版，否则是合并版。
P2 · p02_fig01P2
CH390L (LQFP-48(7x7)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig011929×2637px
CH390L (LQFP-48(7x7)) — V1.8 3
V1.8 3
P34 · p34_fig011390×1386px
CH390L (LQFP-48(7x7)) — CH390 以太网控制器手册 https://wch.cn
CH390 以太网控制器手册 https://wch.cn
P34 · p34_fig01P34
CH390L (LQFP-48(7x7)) — Datasheet Page 34 (p34_fig01)
Datasheet Page 34 (p34_fig01)
P35 · p35_fig011724×1637px
CH390L (LQFP-48(7x7)) — CH390 以太网控制器手册 https://wch.cn
CH390 以太网控制器手册 https://wch.cn
P36 · p36_fig011493×1045px
CH390L (LQFP-48(7x7)) — CH390 以太网控制器手册 https://wch.cn
CH390 以太网控制器手册 https://wch.cn
P36 · p36_fig02927×488px
CH390L (LQFP-48(7x7)) — RXN
RXN

Technical Specifications & Part Details (CH390L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH390L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
72 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH390L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH390L (LQFP-48(7x7))?

Manufactured by WCH, the CH390L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDDK: Power Supply Input (VDDK — 3.3V / 5.0V Standard Logic)), 2 (RSVD.: Multiplexed I/O & Peripheral Pin RSVD. (General)), 3 (MDIRP: Multiplexed I/O & Peripheral Pin MDIRP (General)), 4 (MDIRN: Multiplexed I/O & Peripheral Pin MDIRN (General)), 5 (GND: Ground Reference Pin (GND)), 6 (GND: Ground Reference Pin (GND)).

What are the IPC-7351B PCB Footprint dimensions for CH390L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH390L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH390L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH390L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH390 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDKPower_InPrimary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2RSVD.Digital_IOSignal terminal RSVD. (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD.. Supported peripheral buses: General.
3MDIRPDigital_IOSignal terminal MDIRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRP. Supported peripheral buses: General.
4MDIRNDigital_IOSignal terminal MDIRN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRN. Supported peripheral buses: General.
5GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
6GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
7MDITPDigital_IOSignal terminal MDITP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITP. Supported peripheral buses: General.
8MDITNDigital_IOSignal terminal MDITN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITN. Supported peripheral buses: General.
9RSVD.Digital_IOSignal terminal RSVD. (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD.. Supported peripheral buses: General.
10D7Digital_IOSignal terminal D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D7. Supported peripheral buses: General.
11D6Digital_IOSignal terminal D6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D6. Supported peripheral buses: General.
12D5Digital_IOSignal terminal D5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5. Supported peripheral buses: General.
13D4Digital_IOSignal terminal D4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D4. Supported peripheral buses: General.
14D3Digital_IOSignal terminal D3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D3. Supported peripheral buses: General.
15GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
16D2Digital_IOSignal terminal D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D2. Supported peripheral buses: General.
17D1Digital_IOSignal terminal D1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D1. Supported peripheral buses: General.
18D0Digital_IOSignal terminal D0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D0. Supported peripheral buses: General.
19EEDIODigital_IOSignal terminal EEDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EEDIO. Supported peripheral buses: General.
20EECKDigital_IOSignal terminal EECK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EECK. Supported peripheral buses: General.
21EECS/MD8Digital_IOSignal terminal EECS/MD8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EECS/MD8. Supported peripheral buses: General.
22D15/WOLDigital_IOSignal terminal D15/WOL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D15/WOL. Supported peripheral buses: General.
23AVDD33Power_InPrimary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24D14Digital_IOSignal terminal D14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D14. Supported peripheral buses: General.
25D13/GPIO6Digital_IOSignal terminal D13/GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D13/GPIO6. Supported peripheral buses: General.
26D12/GPIO5Digital_IOSignal terminal D12/GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D12/GPIO5. Supported peripheral buses: General.
27D11/GPIO4Digital_IOSignal terminal D11/GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D11/GPIO4. Supported peripheral buses: General.
28D10/GPIO3Digital_IOSignal terminal D10/GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D10/GPIO3. Supported peripheral buses: General.
29D9/GPIO2Digital_IOSignal terminal D9/GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D9/GPIO2. Supported peripheral buses: General.
30VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
31D8/GPIO1Digital_IOSignal terminal D8/GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D8/GPIO1. Supported peripheral buses: General.
32CMDDigital_IOSignal terminal CMD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CMD. Supported peripheral buses: General.
33GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
34INTDigital_IOSignal terminal INT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT. Supported peripheral buses: General.
35RDBDigital_IOSignal terminal RDB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RDB. Supported peripheral buses: General.
36WRBDigital_IOSignal terminal WRB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WRB. Supported peripheral buses: General.
37CSBDigital_IOSignal terminal CSB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CSB. Supported peripheral buses: General.
38LED2ACTDigital_IOSignal terminal LED2ACT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED2ACT. Supported peripheral buses: General.
39LED1SPDDigital_IOSignal terminal LED1SPD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1SPD. Supported peripheral buses: General.
40RSTBDigital_IOSignal terminal RSTB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTB. Supported peripheral buses: General.
41GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
42AVDD33Power_InPrimary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
43XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
44XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
45GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
46NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
47GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
48GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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