TSSOP-20 · 20P
Synchronized Pinout (Symbol / 2D / 3D) (64/64)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 2 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 3 | GND | GND | Ground Reference Pin (GND) |
| 4 | RXP | I/O | Multiplexed I/O & Peripheral Pin RXP (General) |
| 5 | XO O | I/O | Multiplexed I/O & Peripheral Pin XO O (RTC/CLK) |
| 6 | LINK/RESET I/O PU , | I | System Enable & Hardware Reset (LINK/RESET I/O PU ,) |
| 7 | TXP | I/O | Multiplexed I/O & Peripheral Pin TXP (General) |
| 8 | TXN | I/O | Multiplexed I/O & Peripheral Pin TXN (General) |
| 9 | GND | GND | Ground Reference Pin (GND) |
| 10 | XI | I/O | Multiplexed I/O & Peripheral Pin XI (RTC/CLK) |
| 11 | XO | I/O | Multiplexed I/O & Peripheral Pin XO (RTC/CLK) |
| 12 | TNOW2 | I/O | Multiplexed I/O & Peripheral Pin TNOW2 (General) |
| 13 | GND | GND | Ground Reference Pin (GND) |
| 14 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 15 | CTS | I/O | Multiplexed I/O & Peripheral Pin CTS (UART) |
| 16 | TNOW1/RTS | I/O | Multiplexed I/O & Peripheral Pin TNOW1/RTS (UART) |
| 17 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 18 | GND | GND | Ground Reference Pin (GND) |
| 19 | VDDK | Power | Power Supply Input (VDDK — 3.3V / 5.0V Standard Logic) |
| 20 | GND20 | GND | Ground Reference Pin (GND20) |
| 21 | VCCIO | Power | Power Supply Input (VCCIO — 3.3V / 5.0V Standard Logic) |
| 22 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 23 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 24 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 25 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 26 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 27 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 28 | VDDK | Power | Power Supply Input (VDDK — 3.3V / 5.0V Standard Logic) |
| 29 | VCCIO | Power | Power Supply Input (VCCIO — 3.3V / 5.0V Standard Logic) |
| 30 | TCPCS1 | I/O | Multiplexed I/O & Peripheral Pin TCPCS1 (General) |
| 31 | RUN31 | I/O | Multiplexed I/O & Peripheral Pin RUN31 (General) |
| 32 | CFGEN | I/O | Multiplexed I/O & Peripheral Pin CFGEN (General) |
| 33 | TCPCS2 | I/O | Multiplexed I/O & Peripheral Pin TCPCS2 (General) |
| 34 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 35 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 36 | RSTI | I/O | Multiplexed I/O & Peripheral Pin RSTI (General) |
| 37 | GND | GND | Ground Reference Pin (GND) |
| 38 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 39 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 40 | VCCIO | Power | Power Supply Input (VCCIO — 3.3V / 5.0V Standard Logic) |
| 41 | GND | GND | Ground Reference Pin (GND) |
| 42 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 43 | VDDK | Power | Power Supply Input (VDDK — 3.3V / 5.0V Standard Logic) |
| 44 | GND | GND | Ground Reference Pin (GND) |
| 45 | VCCIO | Power | Power Supply Input (VCCIO — 3.3V / 5.0V Standard Logic) |
| 46 | TNOW2 | I/O | Multiplexed I/O & Peripheral Pin TNOW2 (General) |
| 47 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 48 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 49 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 50 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 51 | TNOW1 | I/O | Multiplexed I/O & Peripheral Pin TNOW1 (General) |
| 52 | ACT | I/O | Multiplexed I/O & Peripheral Pin ACT (General) |
| 53 | LINK | I/O | Multiplexed I/O & Peripheral Pin LINK (General) |
| 54 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 55 | RXD2 | I/O | Multiplexed I/O & Peripheral Pin RXD2 (UART) |
| 56 | TXD2 | I/O | Multiplexed I/O & Peripheral Pin TXD2 (UART) |
| 57 | RXD1 | I/O | Multiplexed I/O & Peripheral Pin RXD1 (UART) |
| 58 | TXD1 | I/O | Multiplexed I/O & Peripheral Pin TXD1 (UART) |
| 59 | RESET | I | System Enable & Hardware Reset (RESET) |
| 60 | CFG | I/O | Multiplexed I/O & Peripheral Pin CFG (General) |
| 61 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 62 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 63 | VCCIO | Power | Power Supply Input (VCCIO — 3.3V / 5.0V Standard Logic) |
| 64 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
PIN 1 NC
I/OMultiplexed I/O & Peripheral Pin NC (General)
Design note: Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-64M(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH9121
P1 · p01_fig011470×859px
P2 · p02_fig011400×747px
P2 · p02_fig01P2
P3 · p03_fig011739×1053px
P12 · p12_fig011365×751px
P12 · p12_fig021083×711px
P13 · p13_fig011648×1373px
P13 · p13_fig021443×905px
P13 · p13_fig01P13
Technical Specifications & Part Details (CH9121A)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH9121A (LQFP-64M(10x10)) is a 64-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25.001
MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64M(10x10))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol64 auto-grouped pins
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH9121 (2)
LQFP-64M(10x10) · 64P
Mechanical Dimensions & Land Pattern (LQFP-64M(10x10))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-64M(10x10) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH9121A (LQFP-64M(10x10))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH9121A (LQFP-64M(10x10))?
Manufactured by WCH, the CH9121A is housed in a LQFP-64M(10x10) package with 64 pins and a 0.50 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (VCC33: Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)), 3 (GND: Ground Reference Pin (GND)), 4 (RXP: Multiplexed I/O & Peripheral Pin RXP (General)), 5 (XO O: Multiplexed I/O & Peripheral Pin XO O (RTC/CLK)), 6 (LINK/RESET I/O PU ,: System Enable & Hardware Reset (LINK/RESET I/O PU ,)).
What are the IPC-7351B PCB Footprint dimensions for CH9121A?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9121A (LQFP-64M(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9121A?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9121A (WCH, LQFP-64M(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (64 pins) & CH9121 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 2 | VCC33 | Power_In | Primary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 3 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | RXP | Digital_IO | Signal terminal RXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXP. Supported peripheral buses: General. |
| 5 | XO O | Digital_IO | Signal terminal XO O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO O. Supported peripheral buses: RTC/CLK. |
| 6 | LINK/RESET I/O PU , | Digital_IO | Active-low hardware reset terminal (LINK/RESET I/O PU ,): pulling this pin Low resets the processor core and peripherals. |
| 7 | TXP | Digital_IO | Signal terminal TXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General. |
| 8 | TXN | Digital_IO | Signal terminal TXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXN. Supported peripheral buses: General. |
| 9 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 10 | XI | Digital_IO | Signal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK. |
| 11 | XO | Digital_IO | Signal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK. |
| 12 | TNOW2 | Digital_IO | Signal terminal TNOW2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW2. Supported peripheral buses: General. |
| 13 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 14 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 15 | CTS | Digital_IO | Signal terminal CTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART. |
| 16 | TNOW1/RTS | Digital_IO | Signal terminal TNOW1/RTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW1/RTS. Supported peripheral buses: UART. |
| 17 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 18 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 19 | VDDK | Power_In | Primary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 20 | GND20 | GND | 0V electrical ground return terminal (GND20) for internal core logic, I/O drivers, and analog sub-blocks. |
| 21 | VCCIO | Power_In | Primary positive power supply input (VCCIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 22 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 23 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 24 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 25 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 26 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 27 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 28 | VDDK | Power_In | Primary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 29 | VCCIO | Power_In | Primary positive power supply input (VCCIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 30 | TCPCS1 | Digital_IO | Signal terminal TCPCS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TCPCS1. Supported peripheral buses: General. |
| 31 | RUN31 | Digital_IO | Signal terminal RUN31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RUN31. Supported peripheral buses: General. |
| 32 | CFGEN | Digital_IO | Signal terminal CFGEN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFGEN. Supported peripheral buses: General. |
| 33 | TCPCS2 | Digital_IO | Signal terminal TCPCS2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TCPCS2. Supported peripheral buses: General. |
| 34 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 35 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 36 | RSTI | Digital_IO | Signal terminal RSTI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTI. Supported peripheral buses: General. |
| 37 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 38 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 39 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 40 | VCCIO | Power_In | Primary positive power supply input (VCCIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 41 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 42 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 43 | VDDK | Power_In | Primary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 44 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 45 | VCCIO | Power_In | Primary positive power supply input (VCCIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 46 | TNOW2 | Digital_IO | Signal terminal TNOW2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW2. Supported peripheral buses: General. |
| 47 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 48 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 49 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 50 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 51 | TNOW1 | Digital_IO | Signal terminal TNOW1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW1. Supported peripheral buses: General. |
| 52 | ACT | Digital_IO | Signal terminal ACT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACT. Supported peripheral buses: General. |
| 53 | LINK | Digital_IO | Signal terminal LINK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LINK. Supported peripheral buses: General. |
| 54 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 55 | RXD2 | Digital_IO | Signal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART. |
| 56 | TXD2 | Digital_IO | Signal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART. |
| 57 | RXD1 | Digital_IO | Signal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART. |
| 58 | TXD1 | Digital_IO | Signal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART. |
| 59 | RESET | Digital_IO | Active-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals. |
| 60 | CFG | Digital_IO | Signal terminal CFG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG. Supported peripheral buses: General. |
| 61 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 62 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 63 | VCCIO | Power_In | Primary positive power supply input (VCCIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 64 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |