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CH318T (TSSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH318T

WCHID: C42387966TSSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH318T (TSSOP-20)1DMX2DPX3XO4XI I5AV P DDK6DMU USB7DPU USB8DM2 USB9DP210IO1 5I/O20NC19NC18NC17NC16V P DD3315GND P14DV P DDK13LED/MODE 5I/12IO311IO2 5I/OGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DMXI/OMultiplexed I/O & Peripheral Pin DMX (General)
2DPXI/OMultiplexed I/O & Peripheral Pin DPX (General)
3XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
4XI II/OMultiplexed I/O & Peripheral Pin XI I (RTC/CLK)
5AV P DDKI/OMultiplexed I/O & Peripheral Pin AV P DDK (General)
6DMU USBI/OMultiplexed I/O & Peripheral Pin DMU USB (USB)
7DPU USBI/OMultiplexed I/O & Peripheral Pin DPU USB (USB)
8DM2 USBI/OMultiplexed I/O & Peripheral Pin DM2 USB (USB)
9DP2I/OMultiplexed I/O & Peripheral Pin DP2 (General)
10IO1 5I/OI/OMultiplexed I/O & Peripheral Pin IO1 5I/O (General)
11IO2 5I/OI/OMultiplexed I/O & Peripheral Pin IO2 5I/O (General)
12IO3I/OMultiplexed I/O & Peripheral Pin IO3 (General)
13LED/MODE 5I/OI/OMultiplexed I/O & Peripheral Pin LED/MODE 5I/O (General)
14DV P DDKI/OMultiplexed I/O & Peripheral Pin DV P DDK (General)
15GND PGNDGround Reference Pin (GND P)
16V P DD33I/OMultiplexed I/O & Peripheral Pin V P DD33 (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18NCI/OMultiplexed I/O & Peripheral Pin NC (General)
19NCI/OMultiplexed I/O & Peripheral Pin NC (General)
20NCI/OMultiplexed I/O & Peripheral Pin NC (General)
PIN 1 DMX
I/O
Multiplexed I/O & Peripheral Pin DMX (General)
Design note: Signal terminal DMX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DMX. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH318T (WCH · TSSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH318T (TSSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH318T (TSSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH318T (TSSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH318T (TSSOP-20) - 4. Package Dimensions (D×E×A)
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH318T (TSSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH318T (TSSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH318
P2 · p02_fig01EXACT PACKAGE
CH318T (TSSOP-20) — 封装形式 塑体尺寸 引脚间距 封装说明 订货型号
封装形式 塑体尺寸 引脚间距 封装说明 订货型号
P2 · p02_fig02EXACT PACKAGE
CH318T (TSSOP-20) — V1.1 2
V1.1 2
P6 · p06_fig01EXACT PACKAGE
CH318T (TSSOP-20) — 7.1 TSSOP20
7.1 TSSOP20
P7 · p07_fig01EXACT PACKAGE
CH318T (TSSOP-20) — 图8-1 CH340T 变压器隔离/延长应用参考电路图
图8-1 CH340T 变压器隔离/延长应用参考电路图
P1 · p01_fig011720×730px
CH318T (TSSOP-20) — 图1-1 CH318 一般应用框图 2、特点
图1-1 CH318 一般应用框图 2、特点
P2 · p02_fig01P2
CH318T (TSSOP-20) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P2 · p02_fig02P2
CH318T (TSSOP-20) — Datasheet Page 2 (p02_fig02)
Datasheet Page 2 (p02_fig02)
P7 · p07_fig01P7
CH318T (TSSOP-20) — Datasheet Page 7 (p07_fig01)
Datasheet Page 7 (p07_fig01)
P8 · p08_fig011424×925px
CH318T (TSSOP-20) — 图8-2 电容隔离/延长应用示意图
图8-2 电容隔离/延长应用示意图

Technical Specifications & Part Details (CH318T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH318T (TSSOP-20) is a 20-pin standard electronic & interconnect component featuring a 6.50 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.00 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH318T (TSSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH318T (TSSOP-20)?

Manufactured by WCH, the CH318T is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch. Key pins include: 1 (DMX: Multiplexed I/O & Peripheral Pin DMX (General)), 2 (DPX: Multiplexed I/O & Peripheral Pin DPX (General)), 3 (XO: Multiplexed I/O & Peripheral Pin XO (RTC/CLK)), 4 (XI I: Multiplexed I/O & Peripheral Pin XI I (RTC/CLK)), 5 (AV P DDK: Multiplexed I/O & Peripheral Pin AV P DDK (General)), 6 (DMU USB: Multiplexed I/O & Peripheral Pin DMU USB (USB)).

What are the IPC-7351B PCB Footprint dimensions for CH318T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH318T (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH318T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH318T (WCH, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH318 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DMXDigital_IOSignal terminal DMX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DMX. Supported peripheral buses: General.
2DPXDigital_IOSignal terminal DPX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DPX. Supported peripheral buses: General.
3XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
4XI IDigital_IOSignal terminal XI I (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI I. Supported peripheral buses: RTC/CLK.
5AV P DDKDigital_IOSignal terminal AV P DDK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AV P DDK. Supported peripheral buses: General.
6DMU USBDigital_IOSignal terminal DMU USB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DMU USB. Supported peripheral buses: USB.
7DPU USBDigital_IOSignal terminal DPU USB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DPU USB. Supported peripheral buses: USB.
8DM2 USBDigital_IOSignal terminal DM2 USB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM2 USB. Supported peripheral buses: USB.
9DP2Digital_IOSignal terminal DP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP2. Supported peripheral buses: General.
10IO1 5I/ODigital_IOSignal terminal IO1 5I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO1 5I/O. Supported peripheral buses: General.
11IO2 5I/ODigital_IOSignal terminal IO2 5I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO2 5I/O. Supported peripheral buses: General.
12IO3Digital_IOSignal terminal IO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO3. Supported peripheral buses: General.
13LED/MODE 5I/ODigital_IOSignal terminal LED/MODE 5I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED/MODE 5I/O. Supported peripheral buses: General.
14DV P DDKDigital_IOSignal terminal DV P DDK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DV P DDK. Supported peripheral buses: General.
15GND PGND0V electrical ground return terminal (GND P) for internal core logic, I/O drivers, and analog sub-blocks.
16V P DD33Digital_IOSignal terminal V P DD33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V P DD33. Supported peripheral buses: General.
17NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
19NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
20NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
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