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CH338L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH338L

WCHID: C42380708LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH338L (LQFP-48(7x7))1LED DRV/_ SM2SDA/ SMBDAT3SCL/ SMBCLK4DP25VDD336DM37DP38DM49DP410GND11DM512DP513DM314DP315VDD3316IO1817DP218DM119DP120PWREN421OVCUR4#22OVCUR3#23PWREN324VDD3348LED547LED646VDD3345OVCUR1234#44PWREN#43OVCUR567#42VDD3341IO4140RESET$39GND38OVCUR6#37OVCUR7#36VDD3335OVCUR5#34DM633DP532IO3231VDD3330DPU29PWREN128OVCUR1#27OVCUR2#26PWREN225DVDDKGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1LED DRV/_ SMB_ENI/OMultiplexed I/O & Peripheral Pin LED DRV/_ SMB_EN (General)
2SDA/ SMBDATI/OMultiplexed I/O & Peripheral Pin SDA/ SMBDAT (I2C)
3SCL/ SMBCLKI/OMultiplexed I/O & Peripheral Pin SCL/ SMBCLK (I2C)
4DP2I/OMultiplexed I/O & Peripheral Pin DP2 (USB)
5VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
6DM3I/OMultiplexed I/O & Peripheral Pin DM3 (USB)
7DP3I/OMultiplexed I/O & Peripheral Pin DP3 (USB)
8DM4I/OMultiplexed I/O & Peripheral Pin DM4 (USB)
9DP4I/OMultiplexed I/O & Peripheral Pin DP4 (USB)
10GNDGNDGround Reference Pin (GND)
11DM5I/OMultiplexed I/O & Peripheral Pin DM5 (USB)
12DP5I/OMultiplexed I/O & Peripheral Pin DP5 (USB)
13DM3I/OMultiplexed I/O & Peripheral Pin DM3 (USB)
14DP3I/OMultiplexed I/O & Peripheral Pin DP3 (USB)
15VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
16IO18I/OGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17DP2I/OMultiplexed I/O & Peripheral Pin DP2 (USB)
18DM1I/OMultiplexed I/O & Peripheral Pin DM1 (USB)
19DP1I/OMultiplexed I/O & Peripheral Pin DP1 (USB)
20PWREN4I/OMultiplexed I/O & Peripheral Pin PWREN4 (General)
21OVCUR4#I/OMultiplexed I/O & Peripheral Pin OVCUR4# (General)
22OVCUR3#I/OMultiplexed I/O & Peripheral Pin OVCUR3# (General)
23PWREN3I/OMultiplexed I/O & Peripheral Pin PWREN3 (General)
24VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
25DVDDKPowerPower Supply Input (DVDDK — 3.3V / 5.0V Standard Logic)
26PWREN2I/OMultiplexed I/O & Peripheral Pin PWREN2 (General)
27OVCUR2#I/OMultiplexed I/O & Peripheral Pin OVCUR2# (General)
28OVCUR1#I/OMultiplexed I/O & Peripheral Pin OVCUR1# (General)
29PWREN1I/OMultiplexed I/O & Peripheral Pin PWREN1 (General)
30DPUI/OMultiplexed I/O & Peripheral Pin DPU (USB)
31VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
32IO32I/OGeneral Purpose Digital I/O Pin IO32
33DP5I/OMultiplexed I/O & Peripheral Pin DP5 (USB)
34DM6I/OMultiplexed I/O & Peripheral Pin DM6 (USB)
35OVCUR5#I/OMultiplexed I/O & Peripheral Pin OVCUR5# (General)
36VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
37OVCUR7#I/OMultiplexed I/O & Peripheral Pin OVCUR7# (General)
38OVCUR6#I/OMultiplexed I/O & Peripheral Pin OVCUR6# (General)
39GNDGNDExposed Thermal & Ground Pad (GND)
40RESET$ISystem Enable & Hardware Reset (RESET$)
41IO41I/OGeneral Purpose Digital I/O Pin IO41
42VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
43OVCUR567#I/OMultiplexed I/O & Peripheral Pin OVCUR567# (General)
44PWREN#I/OMultiplexed I/O & Peripheral Pin PWREN# (General)
45OVCUR1234#I/OMultiplexed I/O & Peripheral Pin OVCUR1234# (General)
46VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
47LED6I/OMultiplexed I/O & Peripheral Pin LED6 (General)
48LED5I/OMultiplexed I/O & Peripheral Pin LED5 (General)
PIN 1 LED DRV/_ SMB_EN
I/O
Multiplexed I/O & Peripheral Pin LED DRV/_ SMB_EN (General)
Design note: Signal terminal LED DRV/_ SMB_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED DRV/_ SMB_EN. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH338L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH338L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH338L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH338L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH338L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH338L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH338L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH338
P3 · p03_fig01EXACT PACKAGE
CH338L (LQFP-48(7x7)) — 3、封装
3、封装
P1 · p01_fig011739×1346px
CH338L (LQFP-48(7x7)) — 图1-1 系统框图
图1-1 系统框图
P10 · p10_fig011368×1179px
CH338L (LQFP-48(7x7)) — 图5-5 CH340X 11 灯模式应用示意图
图5-5 CH340X 11 灯模式应用示意图
P11 · p11_fig011344×252px
CH338L (LQFP-48(7x7)) — CH338 手册 https://wch.cn
CH338 手册 https://wch.cn
P11 · p11_fig021629×1347px
CH338L (LQFP-48(7x7)) — PIN46 PIN47 功能说明 LED7 LED6 0 0 下行端口4、3、2、1 使能。 1 0 下行端口5、4、3、2、1 使能。 0 1 下行端口6、5、4、3、2、1 使能。 1 1 下行端口7、6、5、4、3、2、1 使能。
PIN46 PIN47 功能说明 LED7 LED6 0 0 下行端口4、3、2、1 使能。 1 0 下行端口5、4、3、2、1 使能。 0 1 下行端口6、5、4、3、2、1 使能。 1 1 下行端口7、6、5、4、3、2、1 使能。
P11 · p11_fig031716×1015px
CH338L (LQFP-48(7x7)) — V1.2 11
V1.2 11
P21 · p21_fig011934×1767px
CH338L (LQFP-48(7x7)) — 图8-1 CH338F 总线供电简化示意图
图8-1 CH338F 总线供电简化示意图
P22 · p22_fig012028×1915px
CH338L (LQFP-48(7x7)) — 图8-2 CH338F 自供电简化示意图
图8-2 CH338F 自供电简化示意图
P24 · p24_fig011958×1246px
CH338L (LQFP-48(7x7)) — 图8-4 CH338F 整体过流检测应用图
图8-4 CH338F 整体过流检测应用图
P24 · p24_fig01P24
CH338L (LQFP-48(7x7)) — Datasheet Page 24 (p24_fig01)
Datasheet Page 24 (p24_fig01)

Technical Specifications & Part Details (CH338L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH338L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH338L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH338L (LQFP-48(7x7))?

Manufactured by WCH, the CH338L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (LED DRV/_ SMB_EN: Multiplexed I/O & Peripheral Pin LED DRV/_ SMB_EN (General)), 2 (SDA/ SMBDAT: Multiplexed I/O & Peripheral Pin SDA/ SMBDAT (I2C)), 3 (SCL/ SMBCLK: Multiplexed I/O & Peripheral Pin SCL/ SMBCLK (I2C)), 4 (DP2: Multiplexed I/O & Peripheral Pin DP2 (USB)), 5 (VDD33: Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)), 6 (DM3: Multiplexed I/O & Peripheral Pin DM3 (USB)).

What are the IPC-7351B PCB Footprint dimensions for CH338L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH338L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH338L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH338L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH338 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1LED DRV/_ SMB_ENDigital_IOSignal terminal LED DRV/_ SMB_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED DRV/_ SMB_EN. Supported peripheral buses: General.
2SDA/ SMBDATDigital_IOSignal terminal SDA/ SMBDAT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA/ SMBDAT. Supported peripheral buses: I2C.
3SCL/ SMBCLKDigital_IOSignal terminal SCL/ SMBCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL/ SMBCLK. Supported peripheral buses: I2C.
4DP2Digital_IOSignal terminal DP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP2. Supported peripheral buses: USB.
5VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6DM3Digital_IOSignal terminal DM3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM3. Supported peripheral buses: USB.
7DP3Digital_IOSignal terminal DP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP3. Supported peripheral buses: USB.
8DM4Digital_IOSignal terminal DM4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM4. Supported peripheral buses: USB.
9DP4Digital_IOSignal terminal DP4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP4. Supported peripheral buses: USB.
10GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
11DM5Digital_IOSignal terminal DM5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM5. Supported peripheral buses: USB.
12DP5Digital_IOSignal terminal DP5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP5. Supported peripheral buses: USB.
13DM3Digital_IOSignal terminal DM3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM3. Supported peripheral buses: USB.
14DP3Digital_IOSignal terminal DP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP3. Supported peripheral buses: USB.
15VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
16IO18Digital_IOGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17DP2Digital_IOSignal terminal DP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP2. Supported peripheral buses: USB.
18DM1Digital_IOSignal terminal DM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM1. Supported peripheral buses: USB.
19DP1Digital_IOSignal terminal DP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP1. Supported peripheral buses: USB.
20PWREN4Digital_IOSignal terminal PWREN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN4. Supported peripheral buses: General.
21OVCUR4#Digital_IOSignal terminal OVCUR4# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR4#. Supported peripheral buses: General.
22OVCUR3#Digital_IOSignal terminal OVCUR3# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR3#. Supported peripheral buses: General.
23PWREN3Digital_IOSignal terminal PWREN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN3. Supported peripheral buses: General.
24VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
25DVDDKPower_InPrimary positive power supply input (DVDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
26PWREN2Digital_IOSignal terminal PWREN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN2. Supported peripheral buses: General.
27OVCUR2#Digital_IOSignal terminal OVCUR2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR2#. Supported peripheral buses: General.
28OVCUR1#Digital_IOSignal terminal OVCUR1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR1#. Supported peripheral buses: General.
29PWREN1Digital_IOSignal terminal PWREN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN1. Supported peripheral buses: General.
30DPUDigital_IOSignal terminal DPU (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DPU. Supported peripheral buses: USB.
31VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
32IO32Digital_IOGeneral Purpose Digital I/O Pin IO32
33DP5Digital_IOSignal terminal DP5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP5. Supported peripheral buses: USB.
34DM6Digital_IOSignal terminal DM6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM6. Supported peripheral buses: USB.
35OVCUR5#Digital_IOSignal terminal OVCUR5# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR5#. Supported peripheral buses: General.
36VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
37OVCUR7#Digital_IOSignal terminal OVCUR7# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR7#. Supported peripheral buses: General.
38OVCUR6#Digital_IOSignal terminal OVCUR6# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR6#. Supported peripheral buses: General.
39GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
40RESET$Digital_IOActive-low hardware reset terminal (RESET$): pulling this pin Low resets the processor core and peripherals.
41IO41Digital_IOGeneral Purpose Digital I/O Pin IO41
42VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
43OVCUR567#Digital_IOSignal terminal OVCUR567# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR567#. Supported peripheral buses: General.
44PWREN#Digital_IOSignal terminal PWREN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN#. Supported peripheral buses: General.
45OVCUR1234#Digital_IOSignal terminal OVCUR1234# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR1234#. Supported peripheral buses: General.
46VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
47LED6Digital_IOSignal terminal LED6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED6. Supported peripheral buses: General.
48LED5Digital_IOSignal terminal LED5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED5. Supported peripheral buses: General.
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