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CH334R (QSOP-16-150mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH334R

WCHID: C4154405QSOP-16-150mil · 16 Pins · Pitch 0.64mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH334R (QSOP-16-150mil)1DM42DP43DM34DP35DM26DP27DM18DP116XI15XO14GND13VDD3312V511DPU10DMU9RESET#/CDPGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.215.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
12345678910111213141516E=3.90mm · Pitch e=0.64mmD=4.90mm-5-4-3-2-101234543210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.90mm × 4.90mm · Pitch: 0.64mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (16/16)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DM4I/OMultiplexed I/O & Peripheral Pin DM4 (General)
2DP4I/OMultiplexed I/O & Peripheral Pin DP4 (General)
3DM3I/OMultiplexed I/O & Peripheral Pin DM3 (General)
4DP3I/OMultiplexed I/O & Peripheral Pin DP3 (General)
5DM2I/OMultiplexed I/O & Peripheral Pin DM2 (General)
6DP2I/OMultiplexed I/O & Peripheral Pin DP2 (General)
7DM1I/OMultiplexed I/O & Peripheral Pin DM1 (General)
8DP1I/OMultiplexed I/O & Peripheral Pin DP1 (General)
9RESET#/CDPISystem Enable & Hardware Reset (RESET#/CDP)
10DMUI/OMultiplexed I/O & Peripheral Pin DMU (General)
11DPUI/OMultiplexed I/O & Peripheral Pin DPU (General)
12V5I/OMultiplexed I/O & Peripheral Pin V5 (General)
13VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
14GNDGNDGround Reference Pin (GND)
15XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
16XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
PIN 1 DM4
I/O
Multiplexed I/O & Peripheral Pin DM4 (General)
Design note: Signal terminal DM4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM4. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH334R (WCH · QSOP-16-150mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH334R (QSOP-16-150mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH334R (QSOP-16-150mil) - 2. Standard Pinout (Top View)
True package pinout (16 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH334R (QSOP-16-150mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH334R (QSOP-16-150mil) - 4. Package Dimensions (D×E×A)
QSOP-16-150mil · 3.90×4.90mm · Pitch 0.64mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH334R (QSOP-16-150mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (16 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH334R (QSOP-16-150mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH334 / CH335
P2 · p02_fig01EXACT PACKAGE
CH334R (QSOP-16-150mil) — 图1-1 引脚分布
图1-1 引脚分布
P1 · p01_fig01308×165px
CH334R (QSOP-16-150mil) — 概述
概述
P8 · p08_fig011746×1773px
CH334R (QSOP-16-150mil) — 图3-1-3 持整控独检模 流检测。
图3-1-3 持整控独检模 流检测。
P8 · p08_fig01P8
CH334R (QSOP-16-150mil) — Datasheet Page 8 (p08_fig01)
Datasheet Page 8 (p08_fig01)
P11 · p11_fig011747×519px
CH334R (QSOP-16-150mil) — 图3-2-2 MC
图3-2-2 MC
P26 · p26_fig011762×2211px
CH334R (QSOP-16-150mil) — 工业级应用建议将V5 和VDD33 都接
工业级应用建议将V5 和VDD33 都接
P28 · p28_fig011747×1880px
CH334R (QSOP-16-150mil) — 由于P6 自身及外部电源通常没有负
由于P6 自身及外部电源通常没有负

Technical Specifications & Part Details (CH334R)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH334R (QSOP-16-150mil) is a 16-pin standard electronic & interconnect component featuring a 4.90 × 3.90 × 1.10 mm mechanical envelope (lead pitch e = 0.64 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.90 × 3.90 × 1.10 mm (A1=0.15 mm)
Package family: TSSOP (QSOP-16-150mil)
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 0.64 mm (25.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol16 auto-grouped pins
OK
IPC-7351B Land Pattern16 pads · Pitch 0.64mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QSOP-16-150mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.10mm · e=0.64mm
Pad Size (W × L)Level B
0.38 × 1.50 mm
Pins / Total PadsTopology
16P / 16Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QSOP-16-150mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH334R (QSOP-16-150mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH334R (QSOP-16-150mil)?

Manufactured by WCH, the CH334R is housed in a QSOP-16-150mil package with 16 pins and a 0.64 mm lead pitch. Key pins include: 1 (DM4: Multiplexed I/O & Peripheral Pin DM4 (General)), 2 (DP4: Multiplexed I/O & Peripheral Pin DP4 (General)), 3 (DM3: Multiplexed I/O & Peripheral Pin DM3 (General)), 4 (DP3: Multiplexed I/O & Peripheral Pin DP3 (General)), 5 (DM2: Multiplexed I/O & Peripheral Pin DM2 (General)), 6 (DP2: Multiplexed I/O & Peripheral Pin DP2 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH334R?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH334R (QSOP-16-150mil) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 0.64 mm, and 16 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH334R?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH334R (WCH, QSOP-16-150mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (16 pins) & CH334 / CH335 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DM4Digital_IOSignal terminal DM4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM4. Supported peripheral buses: General.
2DP4Digital_IOSignal terminal DP4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP4. Supported peripheral buses: General.
3DM3Digital_IOSignal terminal DM3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM3. Supported peripheral buses: General.
4DP3Digital_IOSignal terminal DP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP3. Supported peripheral buses: General.
5DM2Digital_IOSignal terminal DM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM2. Supported peripheral buses: General.
6DP2Digital_IOSignal terminal DP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP2. Supported peripheral buses: General.
7DM1Digital_IOSignal terminal DM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM1. Supported peripheral buses: General.
8DP1Digital_IOSignal terminal DP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP1. Supported peripheral buses: General.
9RESET#/CDPDigital_IOActive-low hardware reset terminal (RESET#/CDP): pulling this pin Low resets the processor core and peripherals.
10DMUDigital_IOSignal terminal DMU (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DMU. Supported peripheral buses: General.
11DPUDigital_IOSignal terminal DPU (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DPU. Supported peripheral buses: General.
12V5Digital_IOSignal terminal V5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V5. Supported peripheral buses: General.
13VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
16XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
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