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CH182D (QFN-20(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH182D

WCHID: C41428017QFN-20(3x3) · 21 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH182D (QFN-20(3x3))1TXER2XI33V34MDITN5MDIRP6MDIRN7TXD28IO09IO410TXC /REFCLKI11LED0/PA021RXER /INTB20CRS /LEDMOD19TXD318TXD217TXD116TXD015TXC /REFCLK14NC . (AVDD3313RXC12RXD3 /CLKCTLGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.220.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=3.00mm · Pitch e=0.40mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1TXERI/OMultiplexed I/O & Peripheral Pin TXER (General)
2XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
33V3Power3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4MDITNI/OMultiplexed I/O & Peripheral Pin MDITN (General)
5MDIRPI/OMultiplexed I/O & Peripheral Pin MDIRP (General)
6MDIRNI/OMultiplexed I/O & Peripheral Pin MDIRN (General)
7TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
8IO0I/OGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9IO4I/OGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10TXC /REFCLKII/OMultiplexed I/O & Peripheral Pin TXC /REFCLKI (General)
11LED0/PA0I/OMultiplexed I/O & Peripheral Pin LED0/PA0 (General)
12RXD3 /CLKCTLI/OMultiplexed I/O & Peripheral Pin RXD3 /CLKCTL (UART)
13RXCI/OMultiplexed I/O & Peripheral Pin RXC (UART)
14NC . (AVDD33）PowerPower Supply Input (NC . (AVDD33） — 3.3V / 5.0V Standard Logic)
15TXC /REFCLKI/OMultiplexed I/O & Peripheral Pin TXC /REFCLK (UART)
16TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
17TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
18TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
19TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
20CRS /LEDMODI/OMultiplexed I/O & Peripheral Pin CRS /LEDMOD (General)
21RXER /INTBI/OMultiplexed I/O & Peripheral Pin RXER /INTB (General)
PIN 1 TXER
I/O
Multiplexed I/O & Peripheral Pin TXER (General)
Design note: 发送错误指示 。 晶振输入 ，需外接25MHz 晶体 一端 ，可选外部25MHz 或50MHz
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH182D (WCH · QFN-20(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH182D (QFN-20(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH182D (QFN-20(3x3)) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH182D (QFN-20(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH182D (QFN-20(3x3)) - 4. Package Dimensions (D×E×A)
QFN-20(3x3) · 3.00×3.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH182D (QFN-20(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH182D (QFN-20(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH182
P1 · p01_fig01247×134px
CH182D (QFN-20(3x3)) — 1、概述
1、概述
P1 · p01_fig021687×886px
CH182D (QFN-20(3x3)) — 2、特点
2、特点
P2 · p02_fig011721×2149px
CH182D (QFN-20(3x3)) — 2、新设计可用CH182D/CH182H1/CH182H2，建议优选小体积的CH182D 或CH182H1。 3、客制引脚CH182H3、CH182H6、CH182H7、CH182H8、CH182F2、CH182F7、CH182F8，仅批量预 定，引脚排列和引脚定义请参考《CH182DS3》手册。
2、新设计可用CH182D/CH182H1/CH182H2，建议优选小体积的CH182D 或CH182H1。 3、客制引脚CH182H3、CH182H6、CH182H7、CH182H8、CH182F2、CH182F7、CH182F8，仅批量预 定，引脚排列和引脚定义请参考《CH182DS3》手册。
P32 · p32_fig011598×1580px
CH182D (QFN-20(3x3)) — CH182 以太网PHY 收发器手册 https://wch.cn
CH182 以太网PHY 收发器手册 https://wch.cn
P32 · p32_fig01P32
CH182D (QFN-20(3x3)) — Datasheet Page 32 (p32_fig01)
Datasheet Page 32 (p32_fig01)
P33 · p33_fig011502×1418px
CH182D (QFN-20(3x3)) — CH182 以太网PHY 收发器手册 https://wch.cn
CH182 以太网PHY 收发器手册 https://wch.cn

Technical Specifications & Part Details (CH182D)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH182D (QFN-20(3x3)) is a 20-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, ADC, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
5MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, ADC, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 1.65×1.65mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH182 (3)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-20(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-20(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH182D (QFN-20(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH182D (QFN-20(3x3))?

Manufactured by WCH, the CH182D is housed in a QFN-20(3x3) package with 21 pins and a 0.40 mm lead pitch. Key pins include: 1 (TXER: Multiplexed I/O & Peripheral Pin TXER (General)), 2 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (MDITN: Multiplexed I/O & Peripheral Pin MDITN (General)), 5 (MDIRP: Multiplexed I/O & Peripheral Pin MDIRP (General)), 6 (MDIRN: Multiplexed I/O & Peripheral Pin MDIRN (General)).

What are the IPC-7351B PCB Footprint dimensions for CH182D?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH182D (QFN-20(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.40 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.65 × 1.65 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH182D?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH182D (WCH, QFN-20(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & CH182 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1TXERDigital_IOSignal terminal TXER (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXER. Supported peripheral buses: General.
2XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
33V3Power_In3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4MDITNDigital_IOSignal terminal MDITN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITN. Supported peripheral buses: General.
5MDIRPDigital_IOSignal terminal MDIRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRP. Supported peripheral buses: General.
6MDIRNDigital_IOSignal terminal MDIRN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRN. Supported peripheral buses: General.
7TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
8IO0Digital_IOGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9IO4Digital_IOGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10TXC /REFCLKIDigital_IOSignal terminal TXC /REFCLKI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXC /REFCLKI. Supported peripheral buses: General.
11LED0/PA0Digital_IOSignal terminal LED0/PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED0/PA0. Supported peripheral buses: General.
12RXD3 /CLKCTLDigital_IOSignal terminal RXD3 /CLKCTL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3 /CLKCTL. Supported peripheral buses: UART.
13RXCDigital_IOSignal terminal RXC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXC. Supported peripheral buses: UART.
14NC . (AVDD33）Power_InPrimary positive power supply input (NC . (AVDD33）) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
15TXC /REFCLKDigital_IOSignal terminal TXC /REFCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXC /REFCLK. Supported peripheral buses: UART.
16TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
17TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
18TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
19TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
20CRS /LEDMODDigital_IOSignal terminal CRS /LEDMOD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CRS /LEDMOD. Supported peripheral buses: General.
21RXER /INTBDigital_IOSignal terminal RXER /INTB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXER /INTB. Supported peripheral buses: General.
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