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CH410K (SOT-363) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH410K

WCHID: C39831288SOT-363 · 6 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH410K (SOT-363)1HV2GND3RSTH6VOUT5VCC4RSTLGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.210.25.10-5.1-10.2mm
2. 2D FOOTPRINT
123456E=2.00mm · Pitch e=0.65mmD=1.25mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.00mm × 1.25mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (6/6)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1HVI/OMultiplexed I/O & Peripheral Pin HV (General)
2GNDGNDGround Reference Pin (GND)
3RSTHI/OMultiplexed I/O & Peripheral Pin RSTH (General)
4RSTLI/OMultiplexed I/O & Peripheral Pin RSTL (General)
5VCCPowerRegulated Power Output (VCC — 3.3V / 5.0V Standard Logic)
6VOUTPowerRegulated Power Output (VOUT — 3.3V / 5.0V Standard Logic)
PIN 1 HV
I/O
Multiplexed I/O & Peripheral Pin HV (General)
Design note: 阈值电压设置输入 ： 将HV悬空（不能接GND）选择2 3V低压 . ， 将HV短接到VCC选择3V高压 。 上述为额定值 内部为非精确比较 有离散性 ， ，
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH410K (WCH · SOT-363)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH410K (SOT-363) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH410K (SOT-363) - 2. Standard Pinout (Top View)
True package pinout (6 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH410K (SOT-363) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH410K (SOT-363) - 4. Package Dimensions (D×E×A)
SOT-363 · 2.00×1.25mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH410K (SOT-363) - 5. Recommended Land Pattern
IPC-7351B Footprint (6 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH410K (SOT-363) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH410
P1 · p01_fig02EXACT PACKAGE
CH410K (SOT-363) — 4、引脚
4、引脚
P3 · p03_fig01EXACT PACKAGE
CH410K (SOT-363) — GND
GND
P3 · p03_fig02EXACT PACKAGE
CH410K (SOT-363) — C1 容量不低于2uF，建议大于C2 容量的10 倍。VIN 为供电输入，如果需要更大供电电流，可以 用RSTH 驱动外置P-MOSFET 器件提供1A 以上电流。
C1 容量不低于2uF，建议大于C2 容量的10 倍。VIN 为供电输入，如果需要更大供电电流，可以 用RSTH 驱动外置P-MOSFET 器件提供1A 以上电流。
P1 · p01_fig011550×373px
CH410K (SOT-363) — 2、特点
2、特点
P1 · p01_fig01P1
CH410K (SOT-363) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P4 · p04_fig011210×1386px
CH410K (SOT-363) — CH410 手册 ４
CH410 手册 ４

Technical Specifications & Part Details (CH410K)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH410K (SOT-363) is a 6-pin standard electronic & interconnect component featuring a 2.00 × 1.25 × 0.95 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.00 × 1.25 × 0.95 mm (A1=0.10 mm)
Package family: SOT23 (SOT-363)
Pin Count & Lead PitchN / e
6 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol6 auto-grouped pins
OK
IPC-7351B Land Pattern6 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOT-363)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.00 × 1.25 mm
Height (A) & Pitch (e)IPC-7351B
A=0.95mm · e=0.65mm
Pad Size (W × L)Level B
0.30 × 1.07 mm
Pins / Total PadsTopology
6P / 6Pad (SOT_SMALL)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOT-363
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH410K (SOT-363)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH410K (SOT-363)?

Manufactured by WCH, the CH410K is housed in a SOT-363 package with 6 pins and a 0.65 mm lead pitch. Key pins include: 1 (HV: Multiplexed I/O & Peripheral Pin HV (General)), 2 (GND: Ground Reference Pin (GND)), 3 (RSTH: Multiplexed I/O & Peripheral Pin RSTH (General)), 4 (RSTL: Multiplexed I/O & Peripheral Pin RSTL (General)), 5 (VCC: Regulated Power Output (VCC — 3.3V / 5.0V Standard Logic)), 6 (VOUT: Regulated Power Output (VOUT — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for CH410K?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH410K (SOT-363) has a nominal body envelope of 1.25 × 2.00 mm, pitch e = 0.65 mm, and 6 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH410K?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH410K (WCH, SOT-363) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (6 pins) & CH410 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1HVDigital_IOSignal terminal HV (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV. Supported peripheral buses: General.
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3RSTHDigital_IOSignal terminal RSTH (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTH. Supported peripheral buses: General.
4RSTLDigital_IOSignal terminal RSTL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTL. Supported peripheral buses: General.
5VCCPower_OutRegulated power output rail (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6VOUTPower_OutRegulated power output rail (VOUT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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