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CH224D (QFN-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH224D

WCHID: C3975094QFN-20 · 21 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH224D (QFN-20)1VDD2GND3PG4NC5GATE6CFG7VDD8IO09CFG1 I10IO511CC221GND20NC19CFG118NC17NC16NC15ISN14ISP13CFG212CFG3Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.220.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=3.00mm · Pitch e=0.40mmD=3.00mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
2GNDGNDGround Reference Pin (GND)
3PGI/OMultiplexed I/O & Peripheral Pin PG (General)
4NCI/OMultiplexed I/O & Peripheral Pin NC (General)
5GATEI/OMultiplexed I/O & Peripheral Pin GATE (General)
6CFGI/OMultiplexed I/O & Peripheral Pin CFG (General)
7VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
8IO0I/OGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9CFG1 II/OMultiplexed I/O & Peripheral Pin CFG1 I (General)
10IO5I/OGPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4
11CC2I/OMultiplexed I/O & Peripheral Pin CC2 (General)
12CFG3I/OMultiplexed I/O & Peripheral Pin CFG3 (General)
13CFG2I/OMultiplexed I/O & Peripheral Pin CFG2 (General)
14ISPI/OMultiplexed I/O & Peripheral Pin ISP (General)
15ISNI/OMultiplexed I/O & Peripheral Pin ISN (General)
16NCI/OMultiplexed I/O & Peripheral Pin NC (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18NCI/OMultiplexed I/O & Peripheral Pin NC (General)
19CFG1I/OMultiplexed I/O & Peripheral Pin CFG1 (General)
20NCI/OMultiplexed I/O & Peripheral Pin NC (General)
21GNDGNDGround Reference Pin (GND)
PIN 1 VDD
Power
Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
Design note: 工作电源输入 ，外接1uF 对地电容 ，串联电阻至VBUS 。
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH224D (WCH · QFN-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH224D (QFN-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH224D (QFN-20) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH224D (QFN-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH224D (QFN-20) - 4. Package Dimensions (D×E×A)
QFN-20 · 3.00×3.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH224D (QFN-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH224D (QFN-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for CH221 / CH224
P2 · p02_fig011737×1834px
CH224D (QFN-20) — CH224 手册1 https://wch.cn
CH224 手册1 https://wch.cn
P2 · p02_fig02754×748px
CH224D (QFN-20) — DM 5 CC2 6 CC1 7 VBUS 8 CFG1 9 PG 10 CH224A
DM 5 CC2 6 CC1 7 VBUS 8 CFG1 9 PG 10 CH224A
P8 · p08_fig011624×573px
CH224D (QFN-20) — 6.1.1 单电阻配置和I2C 配置参考原理图（Rset 阻值对应请求电压参考表5-1） 单电阻配置通过CFG1 引脚对GND 接特定阻值的配置电阻实现，此时CFG2 和CFG3 可用于I2C 配 置。若不使用I2C 配置，CFG2、CFG3 悬空即可。 | 6.1.2 I/O 电平配置参考原理图（I/O 电平对应请求电压参考表5-2） 当用电系统无需和CH224 进行交互或控制时，CFG1 可通过串接100KΩ至VHV 引脚的方法提供高 电平（下图为I/O 电平配置20V）
6.1.1 单电阻配置和I2C 配置参考原理图（Rset 阻值对应请求电压参考表5-1） 单电阻配置通过CFG1 引脚对GND 接特定阻值的配置电阻实现，此时CFG2 和CFG3 可用于I2C 配 置。若不使用I2C 配置，CFG2、CFG3 悬空即可。 | 6.1.2 I/O 电平配置参考原理图（I/O 电平对应请求电压参考表5-2） 当用电系统无需和CH224 进行交互或控制时，CFG1 可通过串接100KΩ至VHV 引脚的方法提供高 电平（下图为I/O 电平配置20V）
P8 · p08_fig021545×573px
CH224D (QFN-20) — 当用电系统存在3.3 或5V 电源，且需对CH224 进行控制时，CFG1 可连接系统中MCU 的GPIO（如 下图）。若系统高电平为3.3V，R1 应取0Ω；若系统高电平为5V，R1 应取2KΩ。
当用电系统存在3.3 或5V 电源，且需对CH224 进行控制时，CFG1 可连接系统中MCU 的GPIO（如 下图）。若系统高电平为3.3V，R1 应取0Ω；若系统高电平为5V，R1 应取2KΩ。
P8 · p08_fig031641×572px
CH224D (QFN-20) — V2.1 8
V2.1 8
P9 · p09_fig011341×560px
CH224D (QFN-20) — 6.2 CH224K 参考原理图（图中为I/O 电平配置20V）
6.2 CH224K 参考原理图（图中为I/O 电平配置20V）
P9 · p09_fig021821×751px
CH224D (QFN-20) — 6.1.3 使用Type-C 公口eMarker 模拟功能
6.1.3 使用Type-C 公口eMarker 模拟功能
P9 · p09_fig031834×548px
CH224D (QFN-20) — 6.3 CH224D 参考原理图（图中为单电阻配置9V）
6.3 CH224D 参考原理图（图中为单电阻配置9V）
P9 · p09_fig02P9
CH224D (QFN-20) — Datasheet Page 9 (p09_fig02)
Datasheet Page 9 (p09_fig02)
P10 · p10_fig011270×540px
CH224D (QFN-20) — 6.4 CH221K 参考原理图（图中为单电阻配置20V）
6.4 CH221K 参考原理图（图中为单电阻配置20V）
P10 · p10_fig02525×430px
CH224D (QFN-20) — Rset阻值 请求电压 | 10KΩ 5V 20KΩ 9V 47KΩ 12V 100KΩ 15V 200KΩ 20V
Rset阻值 请求电压 | 10KΩ 5V 20KΩ 9V 47KΩ 12V 100KΩ 15V 200KΩ 20V

Technical Specifications & Part Details (CH224D)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH224D (QFN-20) is a 20-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 1.65×1.65mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.67 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH224D (QFN-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH224D (QFN-20)?

Manufactured by WCH, the CH224D is housed in a QFN-20 package with 21 pins and a 0.40 mm lead pitch. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 2 (GND: Ground Reference Pin (GND)), 3 (PG: Multiplexed I/O & Peripheral Pin PG (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (GATE: Multiplexed I/O & Peripheral Pin GATE (General)), 6 (CFG: Multiplexed I/O & Peripheral Pin CFG (General)).

What are the IPC-7351B PCB Footprint dimensions for CH224D?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH224D (QFN-20) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.40 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.65 × 1.65 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH224D?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH224D (WCH, QFN-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & CH221 / CH224 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3PGDigital_IOSignal terminal PG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG. Supported peripheral buses: General.
4NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
5GATEDigital_IOSignal terminal GATE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GATE. Supported peripheral buses: General.
6CFGDigital_IOSignal terminal CFG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG. Supported peripheral buses: General.
7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
8IO0Digital_IOGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9CFG1 IDigital_IOSignal terminal CFG1 I (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG1 I. Supported peripheral buses: General.
10IO5Digital_IOGPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4
11CC2Digital_IOSignal terminal CC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CC2. Supported peripheral buses: General.
12CFG3Digital_IOSignal terminal CFG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG3. Supported peripheral buses: General.
13CFG2Digital_IOSignal terminal CFG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG2. Supported peripheral buses: General.
14ISPDigital_IOSignal terminal ISP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ISP. Supported peripheral buses: General.
15ISNDigital_IOSignal terminal ISN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ISN. Supported peripheral buses: General.
16NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
17NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
19CFG1Digital_IOSignal terminal CFG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG1. Supported peripheral buses: General.
20NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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