STM32F030R8T6 (LQFP-64(10x10)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of STM32F030R8T6 (LQFP-64(10x10))?

Manufactured by ST, the STM32F030R8T6 is housed in a LQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.4 V to 3.6 V. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (PF0OSC IN -_ (PF0): Multiplexed I/O & Peripheral Pin PF0OSC IN -_ (PF0) (RTC/CLK)), 6 (PF1OSC OUT -_ (PF1): Multiplexed I/O & Peripheral Pin PF1OSC OUT -_ (PF1) (RTC/CLK)).

Q: What are the IPC-7351B PCB Footprint dimensions for STM32F030R8T6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F030R8T6 (LQFP-64(10x10)) has a nominal body envelope of 9.80 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F030R8T6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F030R8T6 (ST, LQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 9.80mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
2	PC13	I/O	Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
3	3V3	Power	3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4	NC	NC	No Connect (Leave Floating)
5	PF0OSC IN -_ (PF0)	I/O	Multiplexed I/O & Peripheral Pin PF0OSC IN -_ (PF0) (RTC/CLK)
6	PF1OSC OUT -_ (PF1)	I/O	Multiplexed I/O & Peripheral Pin PF1OSC OUT -_ (PF1) (RTC/CLK)
7	NRST	I	System Enable & Hardware Reset (NRST)
8	PC0	I/O	Multiplexed I/O & Peripheral Pin PC0 (ADC)
9	PC1	I/O	Multiplexed I/O & Peripheral Pin PC1 (ADC)
10	PC2	I/O	Multiplexed I/O & Peripheral Pin PC2 (ADC)
11	PC3	I/O	Multiplexed I/O & Peripheral Pin PC3 (ADC)
12	VSSA	GND	Ground Reference Pin (VSSA)
13	VDDA	Power	Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))
14	PA0	I/O	Multiplexed I/O & Peripheral Pin PA0 (UART, ADC, RTC/CLK)
15	PA1	I/O	Multiplexed I/O & Peripheral Pin PA1 (UART, ADC)
16	PA2	I/O	Multiplexed I/O & Peripheral Pin PA2 (UART, ADC)
17	PA3	I/O	Multiplexed I/O & Peripheral Pin PA3 (UART, ADC)
18	PF4	I/O	Multiplexed I/O & Peripheral Pin PF4 (General)
19	PF5	I/O	Multiplexed I/O & Peripheral Pin PF5 (General)
20	PA4	I/O	Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
21	PA5	I/O	Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
22	PA6	I/O	Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
23	PA7	I/O	Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
24	PC4	I/O	Multiplexed I/O & Peripheral Pin PC4 (ADC)
25	PC5	I/O	Multiplexed I/O & Peripheral Pin PC5 (ADC)
26	PB0	I/O	Multiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
27	PB1	I/O	Multiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
28	PB2	I/O	Multiplexed I/O & Peripheral Pin PB2 (General)
29	PB10	I/O	Multiplexed I/O & Peripheral Pin PB10 (I2C)
30	PB11	I/O	Multiplexed I/O & Peripheral Pin PB11 (I2C)
31	VSS	GND	Ground Reference Pin (VSS)
32	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
33	PB12	I/O	Multiplexed I/O & Peripheral Pin PB12 (SPI)
34	PB13	I/O	Multiplexed I/O & Peripheral Pin PB13 (SPI, PWM)
35	PB14	I/O	Multiplexed I/O & Peripheral Pin PB14 (SPI, PWM)
36	PB15	I/O	Multiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
37	PC6	I/O	Multiplexed I/O & Peripheral Pin PC6 (PWM)
38	PC7	I/O	Multiplexed I/O & Peripheral Pin PC7 (PWM)
39	PC8	I/O	Multiplexed I/O & Peripheral Pin PC8 (PWM)
40	PC9	I/O	Multiplexed I/O & Peripheral Pin PC9 (PWM)
41	PA8	I/O	Multiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
42	PA9	I/O	Multiplexed I/O & Peripheral Pin PA9 (UART, I2C, PWM)
43	PA10	I/O	Multiplexed I/O & Peripheral Pin PA10 (UART, PWM)
44	PA11	I/O	Multiplexed I/O & Peripheral Pin PA11 (UART, PWM)
45	PA12	I/O	Multiplexed I/O & Peripheral Pin PA12 (UART)
46	PA13 (SWDIO)	I/O	Multiplexed I/O & Peripheral Pin PA13 (SWDIO) (SWD/JTAG)
47	PF6	I/O	Multiplexed I/O & Peripheral Pin PF6 (I2C)
48	PF7	I/O	Multiplexed I/O & Peripheral Pin PF7 (I2C)
49	PA14 (SWCLK)	I/O	Multiplexed I/O & Peripheral Pin PA14 (SWCLK) (UART, SWD/JTAG)
50	PA15	I/O	Multiplexed I/O & Peripheral Pin PA15 (UART, SPI)
51	PC10	I/O	Multiplexed I/O & Peripheral Pin PC10 (General)
52	PC11	I/O	Multiplexed I/O & Peripheral Pin PC11 (General)
53	PC12	I/O	Multiplexed I/O & Peripheral Pin PC12 (General)
54	PD2	I/O	Multiplexed I/O & Peripheral Pin PD2 (General)
55	PB3	I/O	Multiplexed I/O & Peripheral Pin PB3 (SPI)
56	PB4	I/O	Multiplexed I/O & Peripheral Pin PB4 (SPI, PWM)
57	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C, PWM)
58	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (UART, I2C)
59	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (UART, I2C)
60	BOOT0	I	Input-Only Pin BOOT0 (General)
61	PB8	I/O	Multiplexed I/O & Peripheral Pin PB8 (I2C)
62	PB9	I/O	Multiplexed I/O & Peripheral Pin PB9 (I2C)
63	VSS	GND	Ground Reference Pin (VSS)
64	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))

PIN 1 VDD

Power

Power Supply Input (VDD — 3.3V VDD (Max 4.0V))

Design note: Alt: Complementarypowersupply

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 27 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

STM32F030R8T6 (LQFP-64(10x10)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

STM32F030R8T6 (LQFP-64(10x10)) - 2. Standard Pinout (Top View)

True package pinout (64 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

STM32F030R8T6 (LQFP-64(10x10)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

STM32F030R8T6 (LQFP-64(10x10)) - 4. Package Dimensions (D×E×A)

LQFP-64(10x10) · 9.80×10.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

STM32F030R8T6 (LQFP-64(10x10)) - 5. Recommended Land Pattern

IPC-7351B Footprint (64 Pads)Expand ›

6. Application SchematicSCHEMATIC

STM32F030R8T6 (LQFP-64(10x10)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (27 figures · Page 1/3)

Showing 1–12 of 27 uncropped original figures for STM32F030

P23 · p23_fig01EXACT PACKAGE

STM32F030R8T6 (LQFP-64(10x10)) — Figure 3. LQFP64 64-pin package pinout VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28

Figure 3. LQFP64 64-pin package pinout VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28

P75 · p75_fig01EXACT PACKAGE

Figure 26. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline

P76 · p76_fig01EXACT PACKAGE

Figure 27. LQFP64 recommended footprint

P1 · p01_fig01881×507px

STM32F030x8 Value-line ARM-based 32-bit MCU with 16 to 64-KB Flash, timers,

P23 · p23_fig01P23

Datasheet Page 23 (p23_fig01)

P25 · p25_fig011547×720px

Figure 6. TSSOP20 package pinout

P37 · p37_fig011547×1096px

Figure 10. Power supply scheme

P37 · p37_fig01P37

Datasheet Page 37 (p37_fig01)

P51 · p51_fig011547×474px

Figure 14. Typical application with an 8 MHz crystal

P52 · p52_fig011547×734px

Figure 15. Typical application with a 32.768 kHz crystal

P66 · p66_fig011752×902px

Figure 20. ADC accuracy characteristics VDDA

P66 · p66_fig021546×602px

Figure 21. Typical connection diagram using the ADC

Page 1 / 3 (27 extracted figures)

Technical Specifications & Part Details (STM32F030R8T6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Embedded Microcontroller Unit (MCU)

Detailed Overview:STM32F030R8T6 (LQFP-64(10x10)) is a 64-pin embedded microcontroller unit (mcu) featuring a 10.00 × 9.80 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.4 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.

Operating Supply VoltageV_CC / V_DD

2.4 V to 3.6 V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

48 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

36 5V-tolerant (FT) pins detected

Package Envelope (D × E × A)D × E × A

10.00 × 9.80 × 1.60 mm (A1=0.10 mm)

Package family: LQFP (LQFP-64(10x10))

Pin Count & Lead PitchN / e

64 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol64 auto-grouped pins

IPC-7351B Land Pattern64 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

IPC-7351B

Family Variants & Same Datasheet Chips — STM32F030 (11)

Select package variant or sibling MPN sharing this datasheet

TSSOP-20 · 20P

STM32F030F4P6

ST·TSSOP-20

IPC-7351B

20P6.5×4.4×1.20mmP=0.65mm

STM32F030 (TSSOP-20)

TSSOP-20 · 20P

STM32F030F4P6TR

ST·TSSOP-20

IPC-7351B

20P6.5×4.4×1.20mmP=0.65mm

STM32F030 (TSSOP-20)

LQFP-32(7x7) · 32P

STM32F030K6T6

ST·LQFP-32(7x7)

IPC-7351B

32P7.0×7.0×1.60mmP=0.8mm

STM32F030 (LQFP-32(7x7))

LQFP-32(7x7) · 32P

STM32F030K6T6TR

ST·LQFP-32(7x7)

IPC-7351B

32P7.0×7.0×1.60mmP=0.8mm

STM32F030 (LQFP-32(7x7))

LQFP-48(7x7) · 48P

STM32F030C6T6TR

ST·LQFP-48(7x7)

IPC-7351B

48P7.0×7.0×1.60mmP=0.5mm

STM32F030 (LQFP-48(7x7))

LQFP-48(7x7) · 48P

STM32F030C8T6

ST·LQFP-48(7x7)

IPC-7351B

48P7.0×7.0×1.60mmP=0.5mm

STM32F030 (LQFP-48(7x7))

LQFP-48(7x7) · 48P

STM32F030C8T6TR

ST·LQFP-48(7x7)

IPC-7351B

48P7.0×7.0×1.60mmP=0.5mm

STM32F030 (LQFP-48(7x7))

LQFP-48(7x7) · 48P

STM32F030CCT6

ST·LQFP-48(7x7)

IPC-7351B

48P7.0×7.0×1.60mmP=0.5mm

STM32F030 (LQFP-48(7x7))

LQFP-64(10x10) · 64P

STM32F030R8T6

ST·LQFP-64(10x10)

IPC-7351B

64P10.0×9.8×1.60mmP=0.5mm

STM32F030 (LQFP-64(10x10))

LQFP-64(10x10) · 64P

STM32F030R8T6TR

ST·LQFP-64(10x10)

IPC-7351B

64P10.0×10.0×1.60mmP=0.5mm

STM32F030 (LQFP-64(10x10))

LQFP-64(10x10) · 64P

STM32F030RCT6

ST·LQFP-64(10x10)

IPC-7351B

64P10.0×10.0×1.60mmP=0.5mm

STM32F030 (LQFP-64(10x10))

Mechanical Dimensions & Land Pattern (LQFP-64(10x10))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

10.00 × 9.80 mm

Height (A) & Pitch (e)IPC-7351B

A=1.60mm · e=0.50mm

Pad Size (W × L)Level B

0.30 × 1.20 mm

Pins / Total PadsTopology

64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit LQFP-64(10x10)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F030R8T6 (LQFP-64(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F030R8T6 (LQFP-64(10x10))?

Manufactured by ST, the STM32F030R8T6 is housed in a LQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.4 V to 3.6 V. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (PF0OSC IN -_ (PF0): Multiplexed I/O & Peripheral Pin PF0OSC IN -_ (PF0) (RTC/CLK)), 6 (PF1OSC OUT -_ (PF1): Multiplexed I/O & Peripheral Pin PF1OSC OUT -_ (PF1) (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32F030R8T6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F030R8T6 (LQFP-64(10x10)) has a nominal body envelope of 9.80 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F030R8T6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F030R8T6 (ST, LQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32F030 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2	PC13	Digital_IO	Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
3	3V3	Power_In	3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4	NC	No_Connect	No Connect (Leave Floating)
5	PF0OSC IN -_ (PF0)	Digital_IO	Signal terminal PF0OSC IN -_ (PF0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF0OSC IN -_ (PF0). Supported peripheral buses: RTC/CLK.
6	PF1OSC OUT -_ (PF1)	Digital_IO	Signal terminal PF1OSC OUT -_ (PF1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF1OSC OUT -_ (PF1). Supported peripheral buses: RTC/CLK.
7	NRST	Digital_IO	Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8	PC0	Digital_IO	Signal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
9	PC1	Digital_IO	Signal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
10	PC2	Digital_IO	Signal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
11	PC3	Digital_IO	Signal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
12	VSSA	GND	0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
13	VDDA	Power_In	Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
14	PA0	Digital_IO	Signal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, RTC/CLK.
15	PA1	Digital_IO	Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC.
16	PA2	Digital_IO	Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC.
17	PA3	Digital_IO	Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC.
18	PF4	Digital_IO	Signal terminal PF4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
19	PF5	Digital_IO	Signal terminal PF5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
20	PA4	Digital_IO	Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSUSART. Supported peripheral buses: UART, SPI, ADC.
21	PA5	Digital_IO	Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC.
22	PA6	Digital_IO	Signal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC, PWM.
23	PA7	Digital_IO	Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
24	PC4	Digital_IO	Signal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
25	PC5	Digital_IO	Signal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
26	PB0	Digital_IO	Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
27	PB1	Digital_IO	Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
28	PB2	Digital_IO	Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
29	PB10	Digital_IO	Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
30	PB11	Digital_IO	Signal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
31	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
33	PB12	Digital_IO	Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI2_. Supported peripheral buses: SPI.
34	PB13	Digital_IO	Signal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, SPI2_. Supported peripheral buses: SPI, PWM.
35	PB14	Digital_IO	Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI2_. Supported peripheral buses: SPI, PWM.
36	PB15	Digital_IO	Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, SPI2_. Supported peripheral buses: SPI, PWM, RTC/CLK.
37	PC6	Digital_IO	Signal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
38	PC7	Digital_IO	Signal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
39	PC8	Digital_IO	Signal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM.
40	PC9	Digital_IO	Signal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: PWM.
41	PA8	Digital_IO	Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, PWM, RTC/CLK.
42	PA9	Digital_IO	Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, I2C, PWM.
43	PA10	Digital_IO	Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, PWM.
44	PA11	Digital_IO	Signal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART, PWM.
45	PA12	Digital_IO	Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
46	PA13 (SWDIO)	Digital_IO	Signal terminal PA13 (SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (SWDIO). Supported peripheral buses: SWD/JTAG.
47	PF6	Digital_IO	Signal terminal PF6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
48	PF7	Digital_IO	Signal terminal PF7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
49	PA14 (SWCLK)	Digital_IO	Signal terminal PA14 (SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (SWCLK). Supported peripheral buses: UART, SWD/JTAG.
50	PA15	Digital_IO	Signal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSSUSART. Supported peripheral buses: UART, SPI.
51	PC10	Digital_IO	Signal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
52	PC11	Digital_IO	Signal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
53	PC12	Digital_IO	Signal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
54	PD2	Digital_IO	Signal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
55	PB3	Digital_IO	Signal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI.
56	PB4	Digital_IO	Signal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, PWM.
57	PB5	Digital_IO	Signal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C1_SMBA. Supported peripheral buses: SPI, I2C, PWM.
58	PB6	Digital_IO	Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
59	PB7	Digital_IO	Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
60	BOOT0	Digital_IO	Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
61	PB8	Digital_IO	Signal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
62	PB9	Digital_IO	Signal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
63	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
64	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).

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