Mechanical Dimensions & Land Pattern (VSSOP-10)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit VSSOP-10 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — ADS1115IDGSR (VSSOP-10)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of ADS1115IDGSR (VSSOP-10)?
Manufactured by TI, the ADS1115IDGSR is housed in a VSSOP-10 package with 10 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (ADDR: Multiplexed I/O & Peripheral Pin ADDR (I2C)), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (GND: Ground Reference Pin (GND)), 4 (AIN0: Multiplexed I/O & Peripheral Pin AIN0 (ADC)), 5 (AIN1: Multiplexed I/O & Peripheral Pin AIN1 (ADC)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).
What are the IPC-7351B PCB Footprint dimensions for ADS1115IDGSR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ADS1115IDGSR (VSSOP-10) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 10 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ADS1115IDGSR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ADS1115IDGSR (TI, VSSOP-10) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (10 pins) & ADS1115 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | ADDR | Digital_IO | Signal terminal ADDR (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: ADDR. Supported peripheral buses: I2C. |
| 2 | NC | NC | Signal terminal NC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 3 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | AIN0 | Analog | Signal terminal AIN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: AIN0. Supported peripheral buses: ADC. |
| 5 | AIN1 | Analog | Signal terminal AIN1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: AIN1. Supported peripheral buses: ADC. |
| 6 | NC | NC | Signal terminal NC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 7 | NC | NC | Signal terminal NC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 8 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V). |
| 9 | SDA | Digital_IO | Signal terminal SDA (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C. |
| 10 | SCL | Digital_IO | Signal terminal SCL (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C. |