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CH549L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH549L

WCHID: C361810LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH549L (LQFP-48(7x7))102P1.7/SCK/TXD3P5.7/RST4P3.0/RXD5P4.56P4.47P3.1/TXD8P3.2/INT09P3.3/INT110P3.4/T011P3.5/T112P3.6/CAP013P3.7/INT314P4.315P4.216P4.6/XI17XO18GND/VSS19P4.120P4.021P2.0/PWM522P2.1/PWM423P2.2/PWM3/IN24P2.3/PWM248IO4847P1.4/SCS/UCC46P1.3/AIN345P1.2/AIN244P1.1/T2EX/CA43P1.0/T2/CAP142V3341VDD40P0.0/AIN839P0.1/AIN938P0.2/RXD_/AI37P0.3/TXD_/AI36P0.4/RXD2/AI35P0.5/TXD2/AI34P0.6/RXD3/AI33P0.7/TXD3/AI32P5.0/DM31P5.1/DP30P5.4/ALE/CKO29P5.5/HVOD28P2.7/PWM7/TX27P2.6/PWM6/RX26P2.5/PWM0/T225P2.4/PWM1/T2Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
10I/OMultiplexed I/O & Peripheral Pin 0 (General)
2P1.7/SCK/TXD1_/AIN7I/OMultiplexed I/O & Peripheral Pin P1.7/SCK/TXD1_/AIN7 (UART, SPI, ADC)
3P5.7/RSTI/OMultiplexed I/O & Peripheral Pin P5.7/RST (General)
4P3.0/RXDI/OMultiplexed I/O & Peripheral Pin P3.0/RXD (UART)
5P4.5I/OMultiplexed I/O & Peripheral Pin P4.5 (General)
6P4.4I/OMultiplexed I/O & Peripheral Pin P4.4 (General)
7P3.1/TXDI/OMultiplexed I/O & Peripheral Pin P3.1/TXD (UART)
8P3.2/INT0I/OMultiplexed I/O & Peripheral Pin P3.2/INT0 (General)
9P3.3/INT1I/OMultiplexed I/O & Peripheral Pin P3.3/INT1 (General)
10P3.4/T0I/OMultiplexed I/O & Peripheral Pin P3.4/T0 (General)
11P3.5/T1I/OMultiplexed I/O & Peripheral Pin P3.5/T1 (General)
12P3.6/CAP0I/OMultiplexed I/O & Peripheral Pin P3.6/CAP0 (General)
13P3.7/INT3I/OMultiplexed I/O & Peripheral Pin P3.7/INT3 (General)
14P4.3I/OMultiplexed I/O & Peripheral Pin P4.3 (General)
15P4.2I/OMultiplexed I/O & Peripheral Pin P4.2 (General)
16P4.6/XII/OMultiplexed I/O & Peripheral Pin P4.6/XI (RTC/CLK)
17XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
18GND/VSSGNDGround Reference Pin (GND/VSS)
19P4.1I/OMultiplexed I/O & Peripheral Pin P4.1 (General)
20P4.0I/OMultiplexed I/O & Peripheral Pin P4.0 (General)
21P2.0/PWM5I/OMultiplexed I/O & Peripheral Pin P2.0/PWM5 (PWM)
22P2.1/PWM4I/OMultiplexed I/O & Peripheral Pin P2.1/PWM4 (PWM)
23P2.2/PWM3/INT0I/OMultiplexed I/O & Peripheral Pin P2.2/PWM3/INT0 (PWM)
24P2.3/PWM2I/OMultiplexed I/O & Peripheral Pin P2.3/PWM2 (PWM)
25P2.4/PWM1/T2_/CAP1_I/OMultiplexed I/O & Peripheral Pin P2.4/PWM1/T2_/CAP1_ (PWM)
26P2.5/PWM0/T2EX_/CAP2I/OMultiplexed I/O & Peripheral Pin P2.5/PWM0/T2EX_/CAP2 (PWM)
27P2.6/PWM6/RXD1I/OMultiplexed I/O & Peripheral Pin P2.6/PWM6/RXD1 (UART, PWM)
28P2.7/PWM7/TXD1I/OMultiplexed I/O & Peripheral Pin P2.7/PWM7/TXD1 (UART, PWM)
29P5.5/HVODI/OMultiplexed I/O & Peripheral Pin P5.5/HVOD (General)
30P5.4/ALE/CKOI/OMultiplexed I/O & Peripheral Pin P5.4/ALE/CKO (General)
31P5.1/DPI/OMultiplexed I/O & Peripheral Pin P5.1/DP (General)
32P5.0/DMI/OMultiplexed I/O & Peripheral Pin P5.0/DM (General)
33P0.7/TXD3/AIN15I/OMultiplexed I/O & Peripheral Pin P0.7/TXD3/AIN15 (UART, ADC)
34P0.6/RXD3/AIN14I/OMultiplexed I/O & Peripheral Pin P0.6/RXD3/AIN14 (UART, ADC)
35P0.5/TXD2/AIN13I/OMultiplexed I/O & Peripheral Pin P0.5/TXD2/AIN13 (UART, ADC)
36P0.4/RXD2/AIN12I/OMultiplexed I/O & Peripheral Pin P0.4/RXD2/AIN12 (UART, ADC)
37P0.3/TXD_/AIN11I/OMultiplexed I/O & Peripheral Pin P0.3/TXD_/AIN11 (UART, ADC)
38P0.2/RXD_/AIN10I/OMultiplexed I/O & Peripheral Pin P0.2/RXD_/AIN10 (UART, ADC)
39P0.1/AIN9I/OMultiplexed I/O & Peripheral Pin P0.1/AIN9 (ADC)
40P0.0/AIN8I/OMultiplexed I/O & Peripheral Pin P0.0/AIN8 (ADC)
41VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
42V33PowerPower Supply Input (V33 — 3.3V / 5.0V Standard Logic)
43P1.0/T2/CAP1/AIN0I/OMultiplexed I/O & Peripheral Pin P1.0/T2/CAP1/AIN0 (ADC)
44P1.1/T2EX/CAP2/AIN1I/OMultiplexed I/O & Peripheral Pin P1.1/T2EX/CAP2/AIN1 (ADC)
45P1.2/AIN2I/OMultiplexed I/O & Peripheral Pin P1.2/AIN2 (ADC)
46P1.3/AIN3I/OMultiplexed I/O & Peripheral Pin P1.3/AIN3 (ADC)
47P1.4/SCS/UCC1/AIN4I/OMultiplexed I/O & Peripheral Pin P1.4/SCS/UCC1/AIN4 (ADC)
48IO48I/OGeneral Purpose Digital I/O Pin IO48
PIN 1 0
I/O
Multiplexed I/O & Peripheral Pin 0 (General)
Design note: 输出系统主频的4 分频时钟信号 ，即Fsys/4
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH549L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH549L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH549L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH549L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH549L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH549L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH549L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH549
P66 · p66_fig01EXACT PACKAGE
CH549L (LQFP-48(7x7)) — 18.1 LQFP48-7*7 18.2 QFN28-4*4 18.3 SOP16-150mil
18.1 LQFP48-7*7 18.2 QFN28-4*4 18.3 SOP16-150mil
P66 · p66_fig02EXACT PACKAGE
CH549L (LQFP-48(7x7)) — 18.1 LQFP48-7*7 18.2 QFN28-4*4 18.3 SOP16-150mil
18.1 LQFP48-7*7 18.2 QFN28-4*4 18.3 SOP16-150mil
P1 · p01_fig011717×914px
CH549L (LQFP-48(7x7)) — CH549 60KB+3KB 2048 +256 1KB 全/低速 支持 3 组 3 路 8 路 4 组 1 组 16 路 16 通道 CH548 32KB+3KB 2 组
CH549 60KB+3KB 2048 +256 1KB 全/低速 支持 3 组 3 路 8 路 4 组 1 组 16 路 16 通道 CH548 32KB+3KB 2 组
P22 · p22_fig011757×1798px
CH549L (LQFP-48(7x7)) — CH549 手册 22 | 系统时钟配置寄存器(CLOCK_CFG)，仅在安全模式下可写： | 位 名称 访问 描述 复位值 | 7 bOSC_EN_INT RW | 内部时钟振荡器使能，该位为1 使能内部时钟振荡器 并且选用内部时钟；该位为0 关闭内部时钟振荡器并 且选用外部晶体振荡器提供时钟 | 1 | 6 bOSC_EN_XT RW | 外部晶体振荡器使能，该位为1 则P4.6/XO 引脚作为 XI/XO 并启用振荡器，需在XI 和XO 之间外接石英晶 体或陶瓷振荡器；
CH549 手册 22 | 系统时钟配置寄存器(CLOCK_CFG)，仅在安全模式下可写： | 位 名称 访问 描述 复位值 | 7 bOSC_EN_INT RW | 内部时钟振荡器使能，该位为1 使能内部时钟振荡器 并且选用内部时钟；该位为0 关闭内部时钟振荡器并 且选用外部晶体振荡器提供时钟 | 1 | 6 bOSC_EN_XT RW | 外部晶体振荡器使能，该位为1 则P4.6/XO 引脚作为 XI/XO 并启用振荡器，需在XI 和XO 之间外接石英晶 体或陶瓷振荡器；
P22 · p22_fig01P22
CH549L (LQFP-48(7x7)) — Datasheet Page 22 (p22_fig01)
Datasheet Page 22 (p22_fig01)
P27 · p27_fig011757×490px
CH549L (LQFP-48(7x7)) — 由Pn_MOD_OC[x]和Pn_DIR_PU[x]组合实现Pn 端口的相关配置，具体如下。
由Pn_MOD_OC[x]和Pn_DIR_PU[x]组合实现Pn 端口的相关配置，具体如下。
P28 · p28_fig011678×1028px
CH549L (LQFP-48(7x7)) — 图10.2.1 I/O 引脚等效原理图 bPn_MOD_OC[x]
图10.2.1 I/O 引脚等效原理图 bPn_MOD_OC[x]
P64 · p64_fig011757×2757px
CH549L (LQFP-48(7x7)) — CH549 手册 64 | ICMP5 电压比较器模块工作电流 100 500 uA | ITKEY5 触摸按键电容充电电流 35 50 70 uA | VIL5 低电平输入电压 0 1.2 V | VIH5 高电平输入电压 2.4 VDD V | VOL5 低电平输出电压(15mA 吸入电流) 0.4 V | VOH5 高电平输出电压(6mA 输出电流) VDD-0.4 V | VOH5U UDP/UDM 高电平输出电压(8mA 输出电流) V33-0.4 V | VHVO
CH549 手册 64 | ICMP5 电压比较器模块工作电流 100 500 uA | ITKEY5 触摸按键电容充电电流 35 50 70 uA | VIL5 低电平输入电压 0 1.2 V | VIH5 高电平输入电压 2.4 VDD V | VOL5 低电平输出电压(15mA 吸入电流) 0.4 V | VOH5 高电平输出电压(6mA 输出电流) VDD-0.4 V | VOH5U UDP/UDM 高电平输出电压(8mA 输出电流) V33-0.4 V | VHVO
P65 · p65_fig011757×1816px
CH549L (LQFP-48(7x7)) — CH549 手册 65 | Fosc VDD>=3V 时经校准后 | 的内部时钟频率 | TA=-15～65℃ 23.52 24 24.48 MHz | TA=-40～85℃ 23.38 24 24.72 MHz | Fosc3 VDD<3V 时经校准后的内部时钟频率 23.1 24 24.9 MHz | Fpll 内部倍频后的PLL 频率 24 96 96 MHz | Fusb4x 使用USB 主机功能时，USB 采样时钟频率 47.98 48 48.02 MHz | 使用
CH549 手册 65 | Fosc VDD>=3V 时经校准后 | 的内部时钟频率 | TA=-15～65℃ 23.52 24 24.48 MHz | TA=-40～85℃ 23.38 24 24.72 MHz | Fosc3 VDD<3V 时经校准后的内部时钟频率 23.1 24 24.9 MHz | Fpll 内部倍频后的PLL 频率 24 96 96 MHz | Fusb4x 使用USB 主机功能时，USB 采样时钟频率 47.98 48 48.02 MHz | 使用

Technical Specifications & Part Details (CH549L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH549L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
40MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH549L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH549L (LQFP-48(7x7))?

Manufactured by WCH, the CH549L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (0: Multiplexed I/O & Peripheral Pin 0 (General)), 2 (P1.7/SCK/TXD1_/AIN7: Multiplexed I/O & Peripheral Pin P1.7/SCK/TXD1_/AIN7 (UART, SPI, ADC)), 3 (P5.7/RST: Multiplexed I/O & Peripheral Pin P5.7/RST (General)), 4 (P3.0/RXD: Multiplexed I/O & Peripheral Pin P3.0/RXD (UART)), 5 (P4.5: Multiplexed I/O & Peripheral Pin P4.5 (General)), 6 (P4.4: Multiplexed I/O & Peripheral Pin P4.4 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH549L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH549L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH549L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH549L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH549 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
10Digital_IOSignal terminal 0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: 0. Supported peripheral buses: General.
2P1.7/SCK/TXD1_/AIN7Digital_IOSignal terminal P1.7/SCK/TXD1_/AIN7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: UART, SPI, ADC.
3P5.7/RSTDigital_IOSignal terminal P5.7/RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.7/RST. Supported peripheral buses: General.
4P3.0/RXDDigital_IOSignal terminal P3.0/RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.0/RXD. Supported peripheral buses: UART.
5P4.5Digital_IOSignal terminal P4.5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.5. Supported peripheral buses: General.
6P4.4Digital_IOSignal terminal P4.4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.4. Supported peripheral buses: General.
7P3.1/TXDDigital_IOSignal terminal P3.1/TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.1/TXD. Supported peripheral buses: UART.
8P3.2/INT0Digital_IOSignal terminal P3.2/INT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.2/INT0. Supported peripheral buses: General.
9P3.3/INT1Digital_IOSignal terminal P3.3/INT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.3/INT1. Supported peripheral buses: General.
10P3.4/T0Digital_IOSignal terminal P3.4/T0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.4/T0. Supported peripheral buses: General.
11P3.5/T1Digital_IOSignal terminal P3.5/T1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.5/T1. Supported peripheral buses: General.
12P3.6/CAP0Digital_IOSignal terminal P3.6/CAP0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.6/CAP0. Supported peripheral buses: General.
13P3.7/INT3Digital_IOSignal terminal P3.7/INT3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.7/INT3. Supported peripheral buses: General.
14P4.3Digital_IOSignal terminal P4.3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.3. Supported peripheral buses: General.
15P4.2Digital_IOSignal terminal P4.2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.2. Supported peripheral buses: General.
16P4.6/XIDigital_IOSignal terminal P4.6/XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.6/XI. Supported peripheral buses: RTC/CLK.
17XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
18GND/VSSGND0V electrical ground return terminal (GND/VSS) for internal core logic, I/O drivers, and analog sub-blocks.
19P4.1Digital_IOSignal terminal P4.1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.1. Supported peripheral buses: General.
20P4.0Digital_IOSignal terminal P4.0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.0. Supported peripheral buses: General.
21P2.0/PWM5Digital_IOSignal terminal P2.0/PWM5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.0/PWM5. Supported peripheral buses: PWM.
22P2.1/PWM4Digital_IOSignal terminal P2.1/PWM4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.1/PWM4. Supported peripheral buses: PWM.
23P2.2/PWM3/INT0Digital_IOSignal terminal P2.2/PWM3/INT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.2/PWM3/INT0. Supported peripheral buses: PWM.
24P2.3/PWM2Digital_IOSignal terminal P2.3/PWM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.3/PWM2. Supported peripheral buses: PWM.
25P2.4/PWM1/T2_/CAP1_Digital_IOSignal terminal P2.4/PWM1/T2_/CAP1_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.4/PWM1/T2_/CAP1_. Supported peripheral buses: PWM.
26P2.5/PWM0/T2EX_/CAP2Digital_IOSignal terminal P2.5/PWM0/T2EX_/CAP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.5/PWM0/T2EX_/CAP2. Supported peripheral buses: PWM.
27P2.6/PWM6/RXD1Digital_IOSignal terminal P2.6/PWM6/RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.6/PWM6/RXD1. Supported peripheral buses: UART, PWM.
28P2.7/PWM7/TXD1Digital_IOSignal terminal P2.7/PWM7/TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.7/PWM7/TXD1. Supported peripheral buses: UART, PWM.
29P5.5/HVODDigital_IOSignal terminal P5.5/HVOD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.5/HVOD. Supported peripheral buses: General.
30P5.4/ALE/CKODigital_IOSignal terminal P5.4/ALE/CKO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.4/ALE/CKO. Supported peripheral buses: General.
31P5.1/DPDigital_IOSignal terminal P5.1/DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.1/DP. Supported peripheral buses: General.
32P5.0/DMDigital_IOSignal terminal P5.0/DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.0/DM. Supported peripheral buses: General.
33P0.7/TXD3/AIN15Digital_IOSignal terminal P0.7/TXD3/AIN15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.7/TXD3/AIN15. Supported peripheral buses: UART, ADC.
34P0.6/RXD3/AIN14Digital_IOSignal terminal P0.6/RXD3/AIN14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.6/RXD3/AIN14. Supported peripheral buses: UART, ADC.
35P0.5/TXD2/AIN13Digital_IOSignal terminal P0.5/TXD2/AIN13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.5/TXD2/AIN13. Supported peripheral buses: UART, ADC.
36P0.4/RXD2/AIN12Digital_IOSignal terminal P0.4/RXD2/AIN12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.4/RXD2/AIN12. Supported peripheral buses: UART, ADC.
37P0.3/TXD_/AIN11Digital_IOSignal terminal P0.3/TXD_/AIN11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.3/TXD_/AIN11. Supported peripheral buses: UART, ADC.
38P0.2/RXD_/AIN10Digital_IOSignal terminal P0.2/RXD_/AIN10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.2/RXD_/AIN10. Supported peripheral buses: UART, ADC.
39P0.1/AIN9AnalogSignal terminal P0.1/AIN9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.1/AIN9. Supported peripheral buses: ADC.
40P0.0/AIN8AnalogSignal terminal P0.0/AIN8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.0/AIN8. Supported peripheral buses: ADC.
41VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
42V33Power_InPrimary positive power supply input (V33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
43P1.0/T2/CAP1/AIN0AnalogSignal terminal P1.0/T2/CAP1/AIN0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.0/T2/CAP1/AIN0. Supported peripheral buses: ADC.
44P1.1/T2EX/CAP2/AIN1AnalogSignal terminal P1.1/T2EX/CAP2/AIN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.1/T2EX/CAP2/AIN1. Supported peripheral buses: ADC.
45P1.2/AIN2AnalogSignal terminal P1.2/AIN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.2/AIN2. Supported peripheral buses: ADC.
46P1.3/AIN3AnalogSignal terminal P1.3/AIN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.3/AIN3. Supported peripheral buses: ADC.
47P1.4/SCS/UCC1/AIN4AnalogSignal terminal P1.4/SCS/UCC1/AIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.4/SCS/UCC1/AIN4. Supported peripheral buses: ADC.
48IO48Digital_IOGeneral Purpose Digital I/O Pin IO48
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