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HV53001-E/KWX (TFBGA-105(9x9)) — Symbol, Footprint IPC-7351B & 3D STEP Model

HV53001-E/KWX

MICROCHIPID: C3304493TFBGA-105(9x9) · 105 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · HV53001-E/KWX (TFBGA-105(9x9))A1HV 5 OUTA3HV 4 OUTA5HV 3 OUTA7HV 2 OUTA9HV 1 OUTA11HV 0 OUTA13FILPC1HV 6 OUTC3VPPSENSEC4LATCHDC5SSC6SHDNC7V LLC8V CCC9AGNDC10VSSC11VSSPULC13V PPOD3HVGNDD4LATCHCD5SDID6ReservedD7OVPPD8OVPND9FBPD10FBND11VBFBE1HV 7 OUTE3HVGNDE4LATCHBE5SDOE6HVGNDE7ReservedE8NCE9VBOVPE10VLDOE11REFE13V PPF3VNNSENSEF4LATCHAF5SCKF6HVGNDF7STDBYF8SHTENF9SHORTF10TEMPF11AGNDG1HV 8 OUTG3NCG4LATCHING5HVGNDG6HVGNDG7SEQ3N13V NNON11FILNN9HV 15 OUTN7HV 14 OUTN5HV 13 OUTN3HV 12 OUTN1HV 11 OUTL13V NNL11CCP2PL10PGNDL9DL8DL7DL6DL5DL4SL3SL1HV 10 OUTK11CCP2NK10PGNDK9DK8DK7DK6DK5DK4SK3SJ13V NFJ11CCP1PJ10RTJ9ENJ8VDDJ7SHTPJ6DJ5DJ4SJ3SJ1HV 9 OUTH11CCP1NH10TRIGH9T ONH8V INH7SHTNH6HVGNDH5HVGNDH4HVGNDH3NCG13V PFG11CSEQG10SEQ0G9SEQ1G8SEQ2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.873.768.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6-73.7mm
2. 2D FOOTPRINT
A1A3A5A7A9A11A13C1C3C4C5C6C7C8C9C10C11C13D3D4D5D6D7D8D9D10D11E1E3E4E5E6E7E8E9E10E11E13F3F4F5F6F7F8F9F10F11G1G3G4G5G6G7G8G9G10G11G13H3H4H5H6H7H8H9H10H11J1J3J4J5J6J7J8J9J10J11J13K3K4K5K6K7K8K9K10K11L1L3L4L5L6L7L8L9L10L11L13N1N3N5N7N9N11N13E=9.00mm · Pitch e=0.65mmD=9.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 9.00mm × 9.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (105/105)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1HV 5 OUTI/OMultiplexed I/O & Peripheral Pin HV 5 OUT (General)
A3HV 4 OUTI/OMultiplexed I/O & Peripheral Pin HV 4 OUT (General)
A5HV 3 OUTI/OMultiplexed I/O & Peripheral Pin HV 3 OUT (General)
A7HV 2 OUTI/OMultiplexed I/O & Peripheral Pin HV 2 OUT (General)
A9HV 1 OUTI/OMultiplexed I/O & Peripheral Pin HV 1 OUT (General)
A11HV 0 OUTI/OMultiplexed I/O & Peripheral Pin HV 0 OUT (General)
A13FILPI/OMultiplexed I/O & Peripheral Pin FILP (General)
C1HV 6 OUTI/OMultiplexed I/O & Peripheral Pin HV 6 OUT (General)
C3VPPSENSEI/OMultiplexed I/O & Peripheral Pin VPPSENSE (General)
C4LATCHDI/OMultiplexed I/O & Peripheral Pin LATCHD (General)
C5SSI/OMultiplexed I/O & Peripheral Pin SS (SPI)
C6SHDNI/OMultiplexed I/O & Peripheral Pin SHDN (General)
C7V LLI/OMultiplexed I/O & Peripheral Pin V LL (General)
C8V CCI/OMultiplexed I/O & Peripheral Pin V CC (General)
C9AGNDGNDGround Reference Pin (AGND)
C10VSSGNDGround Reference Pin (VSS)
C11VSSPULGNDGround Reference Pin (VSSPUL)
C13V PPOI/OMultiplexed I/O & Peripheral Pin V PPO (General)
D3HVGNDGNDGround Reference Pin (HVGND)
D4LATCHCI/OMultiplexed I/O & Peripheral Pin LATCHC (General)
D5SDII/OMultiplexed I/O & Peripheral Pin SDI (SPI)
D6ReservedI/OMultiplexed I/O & Peripheral Pin Reserved (General)
D7OVPPI/OMultiplexed I/O & Peripheral Pin OVPP (General)
D8OVPNI/OMultiplexed I/O & Peripheral Pin OVPN (General)
D9FBPI/OMultiplexed I/O & Peripheral Pin FBP (General)
D10FBNI/OMultiplexed I/O & Peripheral Pin FBN (General)
D11VBFBI/OMultiplexed I/O & Peripheral Pin VBFB (General)
E1HV 7 OUTI/OMultiplexed I/O & Peripheral Pin HV 7 OUT (General)
E3HVGNDGNDGround Reference Pin (HVGND)
E4LATCHBI/OMultiplexed I/O & Peripheral Pin LATCHB (General)
E5SDOI/OMultiplexed I/O & Peripheral Pin SDO (SPI)
E6HVGNDGNDGround Reference Pin (HVGND)
E7ReservedI/OMultiplexed I/O & Peripheral Pin Reserved (General)
E8NCI/OMultiplexed I/O & Peripheral Pin NC (General)
E9VBOVPI/OMultiplexed I/O & Peripheral Pin VBOVP (General)
E10VLDOI/OMultiplexed I/O & Peripheral Pin VLDO (General)
E11REFI/OMultiplexed I/O & Peripheral Pin REF (General)
E13V PPI/OMultiplexed I/O & Peripheral Pin V PP (General)
F3VNNSENSEI/OMultiplexed I/O & Peripheral Pin VNNSENSE (General)
F4LATCHAI/OMultiplexed I/O & Peripheral Pin LATCHA (General)
F5SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
F6HVGNDGNDGround Reference Pin (HVGND)
F7STDBYI/OMultiplexed I/O & Peripheral Pin STDBY (General)
F8SHTENI/OMultiplexed I/O & Peripheral Pin SHTEN (General)
F9SHORTI/OMultiplexed I/O & Peripheral Pin SHORT (General)
F10TEMPI/OMultiplexed I/O & Peripheral Pin TEMP (General)
F11AGNDGNDGround Reference Pin (AGND)
G1HV 8 OUTI/OMultiplexed I/O & Peripheral Pin HV 8 OUT (General)
G3NCI/OMultiplexed I/O & Peripheral Pin NC (General)
G4LATCHINI/OMultiplexed I/O & Peripheral Pin LATCHIN (SPI)
G5HVGNDGNDGround Reference Pin (HVGND)
G6HVGNDGNDGround Reference Pin (HVGND)
G7SEQ3I/OMultiplexed I/O & Peripheral Pin SEQ3 (General)
G8SEQ2I/OMultiplexed I/O & Peripheral Pin SEQ2 (General)
G9SEQ1I/OMultiplexed I/O & Peripheral Pin SEQ1 (General)
G10SEQ0I/OMultiplexed I/O & Peripheral Pin SEQ0 (General)
G11CSEQI/OMultiplexed I/O & Peripheral Pin CSEQ (General)
G13V PFI/OMultiplexed I/O & Peripheral Pin V PF (General)
H3NCI/OMultiplexed I/O & Peripheral Pin NC (General)
H4HVGNDGNDGround Reference Pin (HVGND)
H5HVGNDGNDGround Reference Pin (HVGND)
H6HVGNDGNDGround Reference Pin (HVGND)
H7SHTNI/OMultiplexed I/O & Peripheral Pin SHTN (General)
H8V INI/OMultiplexed I/O & Peripheral Pin V IN (General)
H9T ONI/OMultiplexed I/O & Peripheral Pin T ON (General)
H10TRIGAnalogMultiplexed I/O & Peripheral Pin TRIG (General)
H11CCP1NI/OMultiplexed I/O & Peripheral Pin CCP1N (General)
J1HV 9 OUTI/OMultiplexed I/O & Peripheral Pin HV 9 OUT (General)
J3SI/OMultiplexed I/O & Peripheral Pin S (General)
J4SI/OMultiplexed I/O & Peripheral Pin S (General)
J5DI/OMultiplexed I/O & Peripheral Pin D (General)
J6DI/OMultiplexed I/O & Peripheral Pin D (General)
J7SHTPI/OMultiplexed I/O & Peripheral Pin SHTP (General)
J8VDDPowerPower Supply Input (VDD — 2.7V-5.5V)
J9ENISystem Enable & Hardware Reset (EN)
J10RTI/OMultiplexed I/O & Peripheral Pin RT (General)
J11CCP1PI/OMultiplexed I/O & Peripheral Pin CCP1P (General)
J13V NFI/OMultiplexed I/O & Peripheral Pin V NF (General)
K3SI/OMultiplexed I/O & Peripheral Pin S (General)
K4SI/OMultiplexed I/O & Peripheral Pin S (General)
K5DI/OMultiplexed I/O & Peripheral Pin D (General)
K6DI/OMultiplexed I/O & Peripheral Pin D (General)
K7DI/OMultiplexed I/O & Peripheral Pin D (General)
K8DI/OMultiplexed I/O & Peripheral Pin D (General)
K9DI/OMultiplexed I/O & Peripheral Pin D (General)
K10PGNDGNDGround Reference Pin (PGND)
K11CCP2NI/OMultiplexed I/O & Peripheral Pin CCP2N (General)
L1HV 10 OUTI/OMultiplexed I/O & Peripheral Pin HV 10 OUT (General)
L3SI/OMultiplexed I/O & Peripheral Pin S (General)
L4SI/OMultiplexed I/O & Peripheral Pin S (General)
L5DI/OMultiplexed I/O & Peripheral Pin D (General)
L6DI/OMultiplexed I/O & Peripheral Pin D (General)
L7DI/OMultiplexed I/O & Peripheral Pin D (General)
L8DI/OMultiplexed I/O & Peripheral Pin D (General)
L9DI/OMultiplexed I/O & Peripheral Pin D (General)
L10PGNDGNDGround Reference Pin (PGND)
L11CCP2PI/OMultiplexed I/O & Peripheral Pin CCP2P (General)
L13V NNI/OMultiplexed I/O & Peripheral Pin V NN (General)
N1HV 11 OUTI/OMultiplexed I/O & Peripheral Pin HV 11 OUT (General)
N3HV 12 OUTI/OMultiplexed I/O & Peripheral Pin HV 12 OUT (General)
N5HV 13 OUTI/OMultiplexed I/O & Peripheral Pin HV 13 OUT (General)
N7HV 14 OUTI/OMultiplexed I/O & Peripheral Pin HV 14 OUT (General)
N9HV 15 OUTI/OMultiplexed I/O & Peripheral Pin HV 15 OUT (General)
N11FILNI/OMultiplexed I/O & Peripheral Pin FILN (General)
N13V NNOI/OMultiplexed I/O & Peripheral Pin V NNO (General)
PIN A1 HV 5 OUT
I/O
Multiplexed I/O & Peripheral Pin HV 5 OUT (General)
Design note: High -Voltage Output 5
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: HV53001-E/KWX (MICROCHIP · TFBGA-105(9x9))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
HV53001-E/KWX (TFBGA-105(9x9)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
HV53001-E/KWX (TFBGA-105(9x9)) - 2. Standard Pinout (Top View)
True package pinout (105 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
HV53001-E/KWX (TFBGA-105(9x9)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
HV53001-E/KWX (TFBGA-105(9x9)) - 4. Package Dimensions (D×E×A)
TFBGA-105(9x9) · 9.00×9.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
HV53001-E/KWX (TFBGA-105(9x9)) - 5. Recommended Land Pattern
IPC-7351B Footprint (105 Pads)Expand ›
6. Application SchematicSCHEMATIC
HV53001-E/KWX (TFBGA-105(9x9)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for HV53001
P1 · p01_fig01376×200px
HV53001-E/KWX (TFBGA-105(9x9)) — 16-Channel, ±135V Push-Pull Driver with RTZ, Current Sensor and Built-in Boost Converter
16-Channel, ±135V Push-Pull Driver with RTZ, Current Sensor and Built-in Boost Converter
P2 · p02_fig011595×1429px
HV53001-E/KWX (TFBGA-105(9x9)) — Typical Application Diagram
Typical Application Diagram
P2 · p02_fig01P2
HV53001-E/KWX (TFBGA-105(9x9)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig011672×1807px
HV53001-E/KWX (TFBGA-105(9x9)) — HV53001
HV53001
P4 · p04_fig011582×1226px
HV53001-E/KWX (TFBGA-105(9x9)) — Block Diagram
Block Diagram
P29 · p29_fig01441×436px
HV53001-E/KWX (TFBGA-105(9x9)) — 105-Ball TFBGA(9x9x1.2 mm) Example
105-Ball TFBGA(9x9x1.2 mm) Example
P29 · p29_fig02441×436px
HV53001-E/KWX (TFBGA-105(9x9)) — 105-Ball TFBGA(9x9x1.2 mm) Example
105-Ball TFBGA(9x9x1.2 mm) Example
P29 · p29_fig01P29
HV53001-E/KWX (TFBGA-105(9x9)) — Datasheet Page 29 (p29_fig01)
Datasheet Page 29 (p29_fig01)

Technical Specifications & Part Details (HV53001-E/KWX)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:HV53001-E/KWX (TFBGA-105(9x9)) is a 105-pin standard electronic & interconnect component featuring a 9.00 × 9.00 × 1.20 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.7V-5.5V supply operation across -40°C to 125°C with integrated SPI interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V-5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.00 × 9.00 × 1.20 mm (A1=0.25 mm)
Package family: BGA (TFBGA-105(9x9))
Pin Count & Lead PitchN / e
105 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol105 auto-grouped pins
OK
IPC-7351B Land Pattern105 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — HV53001 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (TFBGA-105(9x9))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 9.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.65mm
Pad Size (W × L)Level B
0.30 × 0.30 mm
Pins / Total PadsTopology
105P / 105Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-105(9x9)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — HV53001-E/KWX (TFBGA-105(9x9))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of HV53001-E/KWX (TFBGA-105(9x9))?

Manufactured by MICROCHIP, the HV53001-E/KWX is housed in a TFBGA-105(9x9) package with 105 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.7V-5.5V. Key pins include: A1 (HV 5 OUT: Multiplexed I/O & Peripheral Pin HV 5 OUT (General)), A3 (HV 4 OUT: Multiplexed I/O & Peripheral Pin HV 4 OUT (General)), A5 (HV 3 OUT: Multiplexed I/O & Peripheral Pin HV 3 OUT (General)), A7 (HV 2 OUT: Multiplexed I/O & Peripheral Pin HV 2 OUT (General)), A9 (HV 1 OUT: Multiplexed I/O & Peripheral Pin HV 1 OUT (General)), A11 (HV 0 OUT: Multiplexed I/O & Peripheral Pin HV 0 OUT (General)).

What are the IPC-7351B PCB Footprint dimensions for HV53001-E/KWX?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), HV53001-E/KWX (TFBGA-105(9x9)) has a nominal body envelope of 9.00 × 9.00 mm, pitch e = 0.65 mm, and 105 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for HV53001-E/KWX?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for HV53001-E/KWX (MICROCHIP, TFBGA-105(9x9)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (105 pins) & HV53001 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1HV 5 OUTDigital_IOSignal terminal HV 5 OUT (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: HV 5 OUT. Supported peripheral buses: General.
A3HV 4 OUTDigital_IOSignal terminal HV 4 OUT (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: HV 4 OUT. Supported peripheral buses: General.
A5HV 3 OUTDigital_IOSignal terminal HV 3 OUT (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: HV 3 OUT. Supported peripheral buses: General.
A7HV 2 OUTDigital_IOSignal terminal HV 2 OUT (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: HV 2 OUT. Supported peripheral buses: General.
A9HV 1 OUTDigital_IOSignal terminal HV 1 OUT (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: HV 1 OUT. Supported peripheral buses: General.
A11HV 0 OUTDigital_IOSignal terminal HV 0 OUT (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: HV 0 OUT. Supported peripheral buses: General.
A13FILPDigital_IOSignal terminal FILP (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: FILP. Supported peripheral buses: General.
C1HV 6 OUTDigital_IOSignal terminal HV 6 OUT (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: HV 6 OUT. Supported peripheral buses: General.
C3VPPSENSEDigital_IOSignal terminal VPPSENSE (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: VPPSENSE. Supported peripheral buses: General.
C4LATCHDDigital_IOSignal terminal LATCHD (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: LATCHD. Supported peripheral buses: General.
C5SSDigital_IOSignal terminal SS (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SPICHIPSELECT. Supported peripheral buses: SPI.
C6SHDNDigital_IOSignal terminal SHDN (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SHDN. Supported peripheral buses: General.
C7V LLDigital_IOSignal terminal V LL (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: V LL. Supported peripheral buses: General.
C8V CCDigital_IOSignal terminal V CC (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: V CC. Supported peripheral buses: General.
C9AGNDGND0V electrical ground return terminal (AGND) for internal core logic, I/O drivers, and analog sub-blocks.
C10VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C11VSSPULGND0V electrical ground return terminal (VSSPUL) for internal core logic, I/O drivers, and analog sub-blocks.
C13V PPODigital_IOSignal terminal V PPO (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: V PPO. Supported peripheral buses: General.
D3HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
D4LATCHCDigital_IOSignal terminal LATCHC (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: LATCHC. Supported peripheral buses: General.
D5SDIDigital_IOSignal terminal SDI (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SPIDATAIN. Supported peripheral buses: SPI.
D6ReservedDigital_IOSignal terminal Reserved (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: Reserved. Supported peripheral buses: General.
D7OVPPDigital_IOSignal terminal OVPP (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: OVPP. Supported peripheral buses: General.
D8OVPNDigital_IOSignal terminal OVPN (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: OVPN. Supported peripheral buses: General.
D9FBPDigital_IOSignal terminal FBP (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: FBP. Supported peripheral buses: General.
D10FBNDigital_IOSignal terminal FBN (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: FBN. Supported peripheral buses: General.
D11VBFBDigital_IOSignal terminal VBFB (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: VBFB. Supported peripheral buses: General.
E1HV 7 OUTDigital_IOSignal terminal HV 7 OUT (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: HV 7 OUT. Supported peripheral buses: General.
E3HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
E4LATCHBDigital_IOSignal terminal LATCHB (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: LATCHB. Supported peripheral buses: General.
E5SDODigital_IOSignal terminal SDO (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SPIDATAOUT. Supported peripheral buses: SPI.
E6HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
E7ReservedDigital_IOSignal terminal Reserved (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: Reserved. Supported peripheral buses: General.
E8NCNCSignal terminal NC (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
E9VBOVPDigital_IOSignal terminal VBOVP (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: VBOVP. Supported peripheral buses: General.
E10VLDODigital_IOSignal terminal VLDO (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: VLDO. Supported peripheral buses: General.
E11REFDigital_IOSignal terminal REF (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: REF. Supported peripheral buses: General.
E13V PPDigital_IOSignal terminal V PP (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: V PP. Supported peripheral buses: General.
F3VNNSENSEDigital_IOSignal terminal VNNSENSE (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: VNNSENSE. Supported peripheral buses: General.
F4LATCHADigital_IOSignal terminal LATCHA (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: LATCHA. Supported peripheral buses: General.
F5SCKDigital_IOSignal terminal SCK (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SPICLOCK. Supported peripheral buses: SPI.
F6HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
F7STDBYDigital_IOSignal terminal STDBY (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: STDBY. Supported peripheral buses: General.
F8SHTENDigital_IOSignal terminal SHTEN (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SHTEN. Supported peripheral buses: General.
F9SHORTDigital_IOSignal terminal SHORT (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SHORT. Supported peripheral buses: General.
F10TEMPDigital_IOSignal terminal TEMP (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: TEMP. Supported peripheral buses: General.
F11AGNDGND0V electrical ground return terminal (AGND) for internal core logic, I/O drivers, and analog sub-blocks.
G1HV 8 OUTDigital_IOSignal terminal HV 8 OUT (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: HV 8 OUT. Supported peripheral buses: General.
G3NCNCSignal terminal NC (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
G4LATCHINDigital_IOSignal terminal LATCHIN (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SPI_DATA, SPI. Supported peripheral buses: SPI.
G5HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
G6HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
G7SEQ3Digital_IOSignal terminal SEQ3 (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SEQ3. Supported peripheral buses: General.
G8SEQ2Digital_IOSignal terminal SEQ2 (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SEQ2. Supported peripheral buses: General.
G9SEQ1Digital_IOSignal terminal SEQ1 (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SEQ1. Supported peripheral buses: General.
G10SEQ0Digital_IOSignal terminal SEQ0 (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SEQ0. Supported peripheral buses: General.
G11CSEQDigital_IOSignal terminal CSEQ (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: CSEQ. Supported peripheral buses: General.
G13V PFDigital_IOSignal terminal V PF (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: V PF. Supported peripheral buses: General.
H3NCNCSignal terminal NC (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
H4HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
H5HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
H6HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
H7SHTNDigital_IOSignal terminal SHTN (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: SHTN. Supported peripheral buses: General.
H8V INDigital_IOSignal terminal V IN (I/O, 2.7V-5.5V domain). Multiplexed alternate functions: V IN. Supported peripheral buses: General.
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