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ATTINY826-XUR (SSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATTINY826-XUR

MICROCHIPID: C3235604SSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATTINY826-XUR (SSOP-20)1VDD2PA43PA54PA65PA76PB57PB48PB39PB210PB120GND19PA318PA217PA116PA015PC314PC213PC112PC011PB0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=5.30mm · Pitch e=0.65mmD=7.20mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 5.30mm × 7.20mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
2PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
5PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
6PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
7PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
8PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
9PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
10PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
11PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
12PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
13PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
14PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
15PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
16PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
17PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
18PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
19PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
20GNDGNDGround Reference Pin (GND)
PIN 1 VDD
Power
Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATTINY826-XUR (MICROCHIP · SSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATTINY826-XUR (SSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATTINY826-XUR (SSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATTINY826-XUR (SSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATTINY826-XUR (SSOP-20) - 4. Package Dimensions (D×E×A)
SSOP-20 · 5.30×7.20mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATTINY826-XUR (SSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATTINY826-XUR (SSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for ATTINY826
P14 · p14_fig01EXACT PACKAGE
ATTINY826-XUR (SSOP-20) — Pin on VDD Power Domain Analog Function
Pin on VDD Power Domain Analog Function
P520 · p520_fig01EXACT PACKAGE
ATTINY826-XUR (SSOP-20) — Package Drawings
Package Drawings
P1 · p01_fig01456×280px
ATTINY826-XUR (SSOP-20) — Introduction
Introduction
P1 · p01_fig021238×743px
ATTINY826-XUR (SSOP-20) — Figure 1. tinyAVR® 2 Family Overview
Figure 1. tinyAVR® 2 Family Overview
P14 · p14_fig01P14
ATTINY826-XUR (SSOP-20) — Datasheet Page 14 (p14_fig01)
Datasheet Page 14 (p14_fig01)
P513 · p513_fig011320×850px
ATTINY826-XUR (SSOP-20) — RECOMMENDED LAND PATTERN
RECOMMENDED LAND PATTERN
P517 · p517_fig011511×1799px
ATTINY826-XUR (SSOP-20) — Sheet 1 of 2
Sheet 1 of 2
P517 · p517_fig01P517
ATTINY826-XUR (SSOP-20) — Datasheet Page 517 (p517_fig01)
Datasheet Page 517 (p517_fig01)
P518 · p518_fig011595×1637px
ATTINY826-XUR (SSOP-20) — REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances.
P519 · p519_fig011199×1023px
ATTINY826-XUR (SSOP-20) — Units
Units
P519 · p519_fig01P519
ATTINY826-XUR (SSOP-20) — Datasheet Page 519 (p519_fig01)
Datasheet Page 519 (p519_fig01)
P521 · p521_fig011082×927px
ATTINY826-XUR (SSOP-20) — 0.45 0.65
0.45 0.65
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (ATTINY826-XUR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:ATTINY826-XUR (SSOP-20) is a 20-pin standard electronic & interconnect component featuring a 7.20 × 5.30 × 1.85 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C to +85°C with integrated UART, SPI, I2C, ADC, DAC interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.20 × 5.30 × 1.85 mm (A1=0.15 mm)
Package family: TSSOP (SSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, DAC
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.20 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=1.85mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.60 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATTINY826-XUR (SSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATTINY826-XUR (SSOP-20)?

Manufactured by MICROCHIP, the ATTINY826-XUR is housed in a SSOP-20 package with 20 pins and a 0.65 mm lead pitch. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 2 (PA4: Multiplexed I/O & Peripheral Pin PA4 (General)), 3 (PA5: Multiplexed I/O & Peripheral Pin PA5 (General)), 4 (PA6: Multiplexed I/O & Peripheral Pin PA6 (General)), 5 (PA7: Multiplexed I/O & Peripheral Pin PA7 (General)), 6 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)).

What are the IPC-7351B PCB Footprint dimensions for ATTINY826-XUR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATTINY826-XUR (SSOP-20) has a nominal body envelope of 5.30 × 7.20 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATTINY826-XUR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATTINY826-XUR (MICROCHIP, SSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & ATTINY826 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
3PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
5PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
6PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
7PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
8PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
9PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
10PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
11PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
12PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
13PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
14PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
15PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
16PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
17PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
18PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
19PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
20GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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