Mechanical Dimensions & Land Pattern (UDFN-6_L2.0-W2.0-P0.65-BL-EP_MICROCHIP_MT)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit UDFN-6_L2.0-W2.0-P0.65-BL-EP_MICROCHIP_MT | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — FAN5341UMPX-F106 (UDFN-6_L2.0-W2.0-P0.65-BL-EP_MICROCHIP_MT)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of FAN5341UMPX-F106 (UDFN-6_L2.0-W2.0-P0.65-BL-EP_MICROCHIP_MT)?
Manufactured by onsemi, the FAN5341UMPX-F106 is housed in a UDFN-6_L2.0-W2.0-P0.65-BL-EP_MICROCHIP_MT package with 7 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.7 V to 5.5 V. Key pins include: 1 (VOUT: Regulated Power Output (VOUT — 2.7 V to 5.5 V)), 2 (VIN: Power Supply Input (VIN — 2.7 V to 5.5 V)), 3 (EN: System Enable & Hardware Reset (EN)), 4 (FB: Multiplexed I/O & Peripheral Pin FB (General)), 5 (SW: Multiplexed I/O & Peripheral Pin SW (General)), 6 (GND: Ground Reference Pin (GND)).
What are the IPC-7351B PCB Footprint dimensions for FAN5341UMPX-F106?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), FAN5341UMPX-F106 (UDFN-6_L2.0-W2.0-P0.65-BL-EP_MICROCHIP_MT) has a nominal body envelope of 2.00 × 2.00 mm, pitch e = 0.65 mm, and 7 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for FAN5341UMPX-F106?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for FAN5341UMPX-F106 (onsemi, UDFN-6_L2.0-W2.0-P0.65-BL-EP_MICROCHIP_MT) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (7 pins) & FAN5341 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VOUT | Power_Out | Regulated power output rail (VOUT) operating in the 2.7 V to 5.5 V domain (Max rating: 5.5V). |
| 2 | VIN | Power_In | Primary positive power supply input (VIN) operating in the 2.7 V to 5.5 V domain (Max rating: 5.5V). |
| 3 | EN | Digital_IO | Chip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset. |
| 4 | FB | Digital_IO | Signal terminal FB (I/O, 2.7 V to 5.5 V domain). Multiplexed alternate functions: FB. Supported peripheral buses: General. |
| 5 | SW | Digital_IO | Signal terminal SW (I/O, 2.7 V to 5.5 V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General. |
| 6 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 7 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |