QFN-20-EP(2x2) · 21P
Synchronized Pinout (Symbol / 2D / 3D) (33/33)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | CLK | I/O | Multiplexed I/O & Peripheral Pin CLK (General) |
| 2 | NXT | I/O | Multiplexed I/O & Peripheral Pin NXT (General) |
| 3 | D0 | I/O | Multiplexed I/O & Peripheral Pin D0 (General) |
| 4 | D1 | I/O | Multiplexed I/O & Peripheral Pin D1 (General) |
| 5 | D2 | I/O | Multiplexed I/O & Peripheral Pin D2 (General) |
| 6 | D3 | I/O | Multiplexed I/O & Peripheral Pin D3 (General) |
| 7 | D4 | I/O | Multiplexed I/O & Peripheral Pin D4 (General) |
| 8 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 9 | D5 | I/O | Multiplexed I/O & Peripheral Pin D5 (General) |
| 10 | D6 | I/O | Multiplexed I/O & Peripheral Pin D6 (General) |
| 11 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 12 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 13 | D7 | I/O | Multiplexed I/O & Peripheral Pin D7 (General) |
| 14 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 15 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 16 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 17 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 18 | D+ | I/O | Multiplexed I/O & Peripheral Pin D+ (USB) |
| 19 | D- | I/O | Multiplexed I/O & Peripheral Pin D- (USB) |
| 20 | VDD33 | Power | Power Supply Input (VDD33 — 1.8V~3.3V) |
| 21 | V5 | I/O | Multiplexed I/O & Peripheral Pin V5 (General) |
| 22 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 23 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 24 | GND | GND | Ground Reference Pin (GND) |
| 25 | XO | I/O | Multiplexed I/O & Peripheral Pin XO (RTC/CLK) |
| 26 | XI | I/O | Multiplexed I/O & Peripheral Pin XI (RTC/CLK) |
| 27 | RESET# | I | System Enable & Hardware Reset (RESET#) |
| 28 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 29 | STP | I/O | Multiplexed I/O & Peripheral Pin STP (General) |
| 30 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 31 | DIR | I/O | Multiplexed I/O & Peripheral Pin DIR (General) |
| 32 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 33 | EP | GND | Exposed Thermal & Ground Pad (EP) |
PIN 1 CLK
I/OMultiplexed I/O & Peripheral Pin CLK (General)
Design note: Signal terminal CLK (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: CLK. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-32-EP(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH132
P1 · p01_fig01318×170px
P1 · p01_fig021747×872px
P2 · p02_fig011538×2205px
P2 · p02_fig01P2
P3 · p03_fig011838×1608px
P16 · p16_fig011346×1000px
P16 · p16_fig021197×945px
P16 · p16_fig02P16
P19 · p19_fig011729×1187px
P19 · p19_fig01P19
Technical Specifications & Part Details (CH132H)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH132H (QFN-32-EP(5x5)) is a 32-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V~3.3V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V~3.3V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
60MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-32-EP(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol33 auto-grouped pins
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 3.50×3.50mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH132 (3)
QFN-32(5x5) · 33P
QFN-32-EP(5x5) · 33P
Mechanical Dimensions & Land Pattern (QFN-32-EP(5x5))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-32-EP(5x5) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH132H (QFN-32-EP(5x5))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH132H (QFN-32-EP(5x5))?
Manufactured by WCH, the CH132H is housed in a QFN-32-EP(5x5) package with 33 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8V~3.3V. Key pins include: 1 (CLK: Multiplexed I/O & Peripheral Pin CLK (General)), 2 (NXT: Multiplexed I/O & Peripheral Pin NXT (General)), 3 (D0: Multiplexed I/O & Peripheral Pin D0 (General)), 4 (D1: Multiplexed I/O & Peripheral Pin D1 (General)), 5 (D2: Multiplexed I/O & Peripheral Pin D2 (General)), 6 (D3: Multiplexed I/O & Peripheral Pin D3 (General)).
What are the IPC-7351B PCB Footprint dimensions for CH132H?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH132H (QFN-32-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.50 × 3.50 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH132H?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH132H (WCH, QFN-32-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (33 pins) & CH132 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | CLK | Digital_IO | Signal terminal CLK (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: CLK. Supported peripheral buses: General. |
| 2 | NXT | Digital_IO | Signal terminal NXT (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NXT. Supported peripheral buses: General. |
| 3 | D0 | Digital_IO | Signal terminal D0 (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: D0. Supported peripheral buses: General. |
| 4 | D1 | Digital_IO | Signal terminal D1 (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: D1. Supported peripheral buses: General. |
| 5 | D2 | Digital_IO | Signal terminal D2 (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: D2. Supported peripheral buses: General. |
| 6 | D3 | Digital_IO | Signal terminal D3 (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: D3. Supported peripheral buses: General. |
| 7 | D4 | Digital_IO | Signal terminal D4 (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: D4. Supported peripheral buses: General. |
| 8 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 9 | D5 | Digital_IO | Signal terminal D5 (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: D5. Supported peripheral buses: General. |
| 10 | D6 | Digital_IO | Signal terminal D6 (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: D6. Supported peripheral buses: General. |
| 11 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 12 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 13 | D7 | Digital_IO | Signal terminal D7 (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: D7. Supported peripheral buses: General. |
| 14 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 15 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 16 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 17 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 18 | D+ | Digital_IO | Signal terminal D+ (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: D+. Supported peripheral buses: USB. |
| 19 | D- | Digital_IO | Signal terminal D- (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: D-. Supported peripheral buses: USB. |
| 20 | VDD33 | Power_In | Primary positive power supply input (VDD33) operating in the 1.8V~3.3V domain (Max rating: 3.3V). |
| 21 | V5 | Digital_IO | Signal terminal V5 (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: V5. Supported peripheral buses: General. |
| 22 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 23 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 24 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 25 | XO | Digital_IO | Signal terminal XO (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK. |
| 26 | XI | Digital_IO | Signal terminal XI (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK. |
| 27 | RESET# | Digital_IO | Active-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals. |
| 28 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 29 | STP | Digital_IO | Signal terminal STP (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: STP. Supported peripheral buses: General. |
| 30 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 31 | DIR | Digital_IO | Signal terminal DIR (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: DIR. Supported peripheral buses: General. |
| 32 | NC. | Digital_IO | Signal terminal NC. (I/O, 1.8V~3.3V domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 33 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |