QFN-24(4x4) · 25P
Synchronized Pinout (Symbol / 2D / 3D) (25/25)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | ANT | I/O | Multiplexed I/O & Peripheral Pin ANT (General) |
| 2 | VDDA3P3 | Power | Power Supply Input (VDDA3P3 — 3.3V / 5.0V Standard Logic) |
| 3 | VDDA3P3 | Power | Power Supply Input (VDDA3P3 — 3.3V / 5.0V Standard Logic) |
| 4 | GPIO0 | I/O | Multiplexed I/O & Peripheral Pin GPIO0 (ADC) |
| 5 | GPIO1 | I/O | Multiplexed I/O & Peripheral Pin GPIO1 (ADC) |
| 6 | GPIO2 | I/O | Multiplexed I/O & Peripheral Pin GPIO2 (SPI, ADC) |
| 7 | CHIP_EN | I/O | Multiplexed I/O & Peripheral Pin CHIP_EN (General) |
| 8 | GPIO3 | I/O | Multiplexed I/O & Peripheral Pin GPIO3 (ADC) |
| 9 | MTMS | I/O | Multiplexed I/O & Peripheral Pin MTMS (SPI, ADC, SWD/JTAG) |
| 10 | MTDI | I/O | Multiplexed I/O & Peripheral Pin MTDI (SPI, SWD/JTAG) |
| 11 | VDD3P3_RTC | Power | Power Supply Input (VDD3P3_RTC — 3.3V / 5.0V Standard Logic) |
| 12 | MTCK | I/O | Multiplexed I/O & Peripheral Pin MTCK (SPI, SWD/JTAG) |
| 13 | MTDO | I/O | Multiplexed I/O & Peripheral Pin MTDO (SPI, SWD/JTAG) |
| 14 | GPIO8 | I/O | Multiplexed I/O & Peripheral Pin GPIO8 (General) |
| 15 | GPIO9 | I/O | Multiplexed I/O & Peripheral Pin GPIO9 (General) |
| 16 | GPIO10 | I/O | Multiplexed I/O & Peripheral Pin GPIO10 (SPI) |
| 17 | VDD3P3_CPU | Power | Power Supply Input (VDD3P3_CPU — 3.3V / 5.0V Standard Logic) |
| 18 | GPIO18 | I/O | Multiplexed I/O & Peripheral Pin GPIO18 (General) |
| 19 | U0RXD | I/O | Multiplexed I/O & Peripheral Pin U0RXD (UART) |
| 20 | U0TXD | I/O | Multiplexed I/O & Peripheral Pin U0TXD (UART) |
| 21 | VDDA | Power | Power Supply Input (VDDA — 3.3V / 5.0V Standard Logic) |
| 22 | XTAL_N | I/O | Multiplexed I/O & Peripheral Pin XTAL_N (RTC/CLK) |
| 23 | XTAL_P | I/O | Multiplexed I/O & Peripheral Pin XTAL_P (RTC/CLK) |
| 24 | VDDA | Power | Power Supply Input (VDDA — 3.3V / 5.0V Standard Logic) |
| 25 | GND | GND | Ground Reference Pin (GND) |
PIN 1 ANT
I/OMultiplexed I/O & Peripheral Pin ANT (General)
Design note: 射频输入和输出
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (25 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-24(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (25 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for ESP8684
P35 · p35_fig01EXACT PACKAGE
P1 · p01_fig01646×314px
P2 · p02_fig011562×1437px
P10 · p10_fig011378×1295px
P10 · p10_fig02685×222px
P10 · p10_fig01P10
P12 · p12_fig011827×1333px
P12 · p12_fig021593×529px
P38 · p38_fig011759×754px
Technical Specifications & Part Details (ESP8684H4)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:ESP8684H4 (QFN-24(4x4)) is a 24-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, Bluetooth / BLE, UART, SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
500 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-24(4x4))
Pin Count & Lead PitchN / e
24 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, UART, SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (GPIO0, MTDI, MTDO): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol25 auto-grouped pins
IPC-7351B Land Pattern25 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 2.80×2.80mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — ESP8684 (3)
QFN-24(4x4) · 25P
QFN-24(4x4) · 25P
Mechanical Dimensions & Land Pattern (QFN-24(4x4))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
25P / 25Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-24(4x4) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — ESP8684H4 (QFN-24(4x4))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of ESP8684H4 (QFN-24(4x4))?
Manufactured by ESPRESSIF, the ESP8684H4 is housed in a QFN-24(4x4) package with 25 pins and a 0.50 mm lead pitch. Key pins include: 1 (ANT: Multiplexed I/O & Peripheral Pin ANT (General)), 2 (VDDA3P3: Power Supply Input (VDDA3P3 — 3.3V / 5.0V Standard Logic)), 3 (VDDA3P3: Power Supply Input (VDDA3P3 — 3.3V / 5.0V Standard Logic)), 4 (GPIO0: Multiplexed I/O & Peripheral Pin GPIO0 (ADC)), 5 (GPIO1: Multiplexed I/O & Peripheral Pin GPIO1 (ADC)), 6 (GPIO2: Multiplexed I/O & Peripheral Pin GPIO2 (SPI, ADC)).
What are the IPC-7351B PCB Footprint dimensions for ESP8684H4?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP8684H4 (QFN-24(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 25 copper pads plus a central exposed thermal pad (EPAD) of 2.80 × 2.80 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP8684H4?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP8684H4 (ESPRESSIF, QFN-24(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (25 pins) & ESP8684 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | ANT | RF_50Ohm | Signal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General. |
| 2 | VDDA3P3 | Power_In | Primary positive power supply input (VDDA3P3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 3 | VDDA3P3 | Power_In | Primary positive power supply input (VDDA3P3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 4 | GPIO0 | Digital_IO | Signal terminal GPIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ADC1_CH0. Supported peripheral buses: ADC. |
| 5 | GPIO1 | Digital_IO | Signal terminal GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ADC1_CH1. Supported peripheral buses: ADC. |
| 6 | GPIO2 | Digital_IO | Signal terminal GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ADC1_CH2, FSPIQ. Supported peripheral buses: SPI, ADC. |
| 7 | CHIP_EN | Digital_IO | Signal terminal CHIP_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CHIP_EN. Supported peripheral buses: General. |
| 8 | GPIO3 | Digital_IO | Signal terminal GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ADC1_CH3. Supported peripheral buses: ADC. |
| 9 | MTMS | Digital_IO | Signal terminal MTMS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO4, ADC1_CH4, FSPIHD. Supported peripheral buses: SPI, ADC, SWD/JTAG. |
| 10 | MTDI | Digital_IO | Signal terminal MTDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO5, FSPIWP. Supported peripheral buses: SPI, SWD/JTAG. |
| 11 | VDD3P3_RTC | Power_In | Primary positive power supply input (VDD3P3_RTC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 12 | MTCK | Digital_IO | Signal terminal MTCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO6, FSPICLK. Supported peripheral buses: SPI, SWD/JTAG. |
| 13 | MTDO | Digital_IO | Signal terminal MTDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO7, FSPID. Supported peripheral buses: SPI, SWD/JTAG. |
| 14 | GPIO8 | Digital_IO | Signal terminal GPIO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General. |
| 15 | GPIO9 | Digital_IO | Signal terminal GPIO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General. |
| 16 | GPIO10 | Digital_IO | Signal terminal GPIO10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FSPICS0. Supported peripheral buses: SPI. |
| 17 | VDD3P3_CPU | Power_In | Primary positive power supply input (VDD3P3_CPU) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 18 | GPIO18 | Digital_IO | Signal terminal GPIO18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO18. Supported peripheral buses: General. |
| 19 | U0RXD | Digital_IO | Signal terminal U0RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO19. Supported peripheral buses: UART. |
| 20 | U0TXD | Digital_IO | Signal terminal U0TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO20. Supported peripheral buses: UART. |
| 21 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 22 | XTAL_N | Digital_IO | Signal terminal XTAL_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_N. Supported peripheral buses: RTC/CLK. |
| 23 | XTAL_P | Digital_IO | Signal terminal XTAL_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_P. Supported peripheral buses: RTC/CLK. |
| 24 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 25 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |