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ESP32-S2R2 (VFQFN-56-EP) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP32-S2R2

ESPRESSIFID: C3013903VFQFN-56-EP · 57 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP32-S2R2 (VFQFN-56-EP)1VDDA2LNA_IN3VDD3P34VDD3P35GPIO06GPIO17GPIO28GPIO39GPIO410GPIO511GPIO612GPIO713GPIO814GPIO915GPIO1016GPIO1117GPIO1218GPIO1319GPIO1420VDD3P3_RTC21XTAL_32KP_22XTAL_32KN_23DAC_124DAC_225GPIO1926GPIO2027VDD3P3_RTCIO28GPIO2129SPICS157GND56CHIP_PU55GPIO4654VDDA53XTAL_P52XTAL_N51VDDA50GPIO4549U0RXD48U0TXD47MTMS46MTDI45VDD3P3_CPU44MTDO43MTCK42GPIO3841GPIO3740GPIO3639GPIO3538GPIO3437GPIO3336SPID35SPIQ34SPICLK33SPICS032SPIWP31SPIHD30VDD_SPIGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.843.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657E=7.00mm · Pitch e=0.40mmD=7.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (57/57)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDAPowerPower Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
2LNA_INI/OMultiplexed I/O & Peripheral Pin LNA_IN (General)
3VDD3P3PowerPower Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
4VDD3P3PowerPower Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
5GPIO0I/OMultiplexed I/O & Peripheral Pin GPIO0 (RTC/CLK)
6GPIO1I/OMultiplexed I/O & Peripheral Pin GPIO1 (RTC/CLK, TOUCH)
7GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (RTC/CLK, TOUCH)
8GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (RTC/CLK, TOUCH)
9GPIO4I/OMultiplexed I/O & Peripheral Pin GPIO4 (RTC/CLK, TOUCH)
10GPIO5I/OMultiplexed I/O & Peripheral Pin GPIO5 (RTC/CLK, TOUCH)
11GPIO6I/OMultiplexed I/O & Peripheral Pin GPIO6 (RTC/CLK, TOUCH)
12GPIO7I/OMultiplexed I/O & Peripheral Pin GPIO7 (RTC/CLK, TOUCH)
13GPIO8I/OMultiplexed I/O & Peripheral Pin GPIO8 (RTC/CLK, TOUCH)
14GPIO9I/OMultiplexed I/O & Peripheral Pin GPIO9 (ADC, RTC/CLK, TOUCH)
15GPIO10I/OMultiplexed I/O & Peripheral Pin GPIO10 (ADC, RTC/CLK, TOUCH)
16GPIO11I/OMultiplexed I/O & Peripheral Pin GPIO11 (ADC, RTC/CLK, TOUCH)
17GPIO12I/OMultiplexed I/O & Peripheral Pin GPIO12 (ADC, RTC/CLK, TOUCH)
18GPIO13I/OMultiplexed I/O & Peripheral Pin GPIO13 (ADC, RTC/CLK, TOUCH)
19GPIO14I/OMultiplexed I/O & Peripheral Pin GPIO14 (ADC, RTC/CLK, TOUCH)
20VDD3P3_RTCPowerPower Supply Input (VDD3P3_RTC — 3.3V VDD3P3 (3.0V ~ 3.6V))
21XTAL_32KP_I/OMultiplexed I/O & Peripheral Pin XTAL_32KP_ (ADC, RTC/CLK)
22XTAL_32KN_I/OMultiplexed I/O & Peripheral Pin XTAL_32KN_ (ADC, RTC/CLK)
23DAC_1I/OMultiplexed I/O & Peripheral Pin DAC_1 (UART, ADC, DAC, RTC/CLK)
24DAC_2I/OMultiplexed I/O & Peripheral Pin DAC_2 (UART, ADC, DAC, RTC/CLK)
25GPIO19I/OMultiplexed I/O & Peripheral Pin GPIO19 (ADC, RTC/CLK)
26GPIO20I/OMultiplexed I/O & Peripheral Pin GPIO20 (USB, ADC, RTC/CLK)
27VDD3P3_RTCIO_PowerPower Supply Input (VDD3P3_RTCIO_ — 3.3V VDD3P3 (3.0V ~ 3.6V))
28GPIO21I/OMultiplexed I/O & Peripheral Pin GPIO21 (RTC/CLK)
29SPICS1I/OMultiplexed I/O & Peripheral Pin SPICS1 (SPI)
30VDD_SPIPowerRegulated Power Output (VDD_SPI — 3.3V VDD3P3 (3.0V ~ 3.6V))
31SPIHDI/OMultiplexed I/O & Peripheral Pin SPIHD (SPI)
32SPIWPI/OMultiplexed I/O & Peripheral Pin SPIWP (SPI)
33SPICS0I/OMultiplexed I/O & Peripheral Pin SPICS0 (SPI)
34SPICLKI/OMultiplexed I/O & Peripheral Pin SPICLK (SPI)
35SPIQI/OMultiplexed I/O & Peripheral Pin SPIQ (SPI)
36SPIDI/OMultiplexed I/O & Peripheral Pin SPID (SPI)
37GPIO33I/OMultiplexed I/O & Peripheral Pin GPIO33 (SPI)
38GPIO34I/OMultiplexed I/O & Peripheral Pin GPIO34 (SPI)
39GPIO35I/OMultiplexed I/O & Peripheral Pin GPIO35 (SPI)
40GPIO36I/OMultiplexed I/O & Peripheral Pin GPIO36 (SPI)
41GPIO37I/OMultiplexed I/O & Peripheral Pin GPIO37 (SPI)
42GPIO38I/OMultiplexed I/O & Peripheral Pin GPIO38 (SPI)
43MTCKI/OMultiplexed I/O & Peripheral Pin MTCK (SWD/JTAG)
44MTDOI/OMultiplexed I/O & Peripheral Pin MTDO (SWD/JTAG)
45VDD3P3_CPUPowerPower Supply Input (VDD3P3_CPU — 3.3V VDD3P3 (3.0V ~ 3.6V))
46MTDII/OMultiplexed I/O & Peripheral Pin MTDI (SWD/JTAG)
47MTMSI/OMultiplexed I/O & Peripheral Pin MTMS (SWD/JTAG)
48U0TXDI/OMultiplexed I/O & Peripheral Pin U0TXD (UART)
49U0RXDI/OMultiplexed I/O & Peripheral Pin U0RXD (UART)
50GPIO45I/OMultiplexed I/O & Peripheral Pin GPIO45 (General)
51VDDAPowerPower Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
52XTAL_NI/OMultiplexed I/O & Peripheral Pin XTAL_N (RTC/CLK)
53XTAL_PI/OMultiplexed I/O & Peripheral Pin XTAL_P (RTC/CLK)
54VDDAPowerPower Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
55GPIO46I/OMultiplexed I/O & Peripheral Pin GPIO46 (General)
56CHIP_PUISystem Enable & Hardware Reset (CHIP_PU)
57GNDGNDExposed Thermal & Ground Pad (GND)
PIN 1 VDDA
Power
Power Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
Design note: 模拟电源
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP32-S2R2 (ESPRESSIF · VFQFN-56-EP)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP32-S2R2 (VFQFN-56-EP) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP32-S2R2 (VFQFN-56-EP) - 2. Standard Pinout (Top View)
True package pinout (57 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP32-S2R2 (VFQFN-56-EP) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP32-S2R2 (VFQFN-56-EP) - 4. Package Dimensions (D×E×A)
VFQFN-56-EP · 7.00×7.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP32-S2R2 (VFQFN-56-EP) - 5. Recommended Land Pattern
IPC-7351B Footprint (57 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP32-S2R2 (VFQFN-56-EP) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for ESP32-S2 / ESP32-S2FH2 / ESP32-S2FH4
P43 · p43_fig01EXACT PACKAGE
ESP32-S2R2 (VFQFN-56-EP) — 图9: QFN56 (7×7 mm) 封装，用于ESP32-S2FN4R2
图9: QFN56 (7×7 mm) 封装，用于ESP32-S2FN4R2
P1 · p01_fig01645×314px
ESP32-S2R2 (VFQFN-56-EP) — www.espressif.com
www.espressif.com
P12 · p12_fig011345×1396px
ESP32-S2R2 (VFQFN-56-EP) — 图3: ESP32-S2 系列芯片管脚布局（俯视图）
图3: ESP32-S2 系列芯片管脚布局（俯视图）
P12 · p12_fig02795×258px
ESP32-S2R2 (VFQFN-56-EP) — ESP32-S2
ESP32-S2
P12 · p12_fig01P12
ESP32-S2R2 (VFQFN-56-EP) — Datasheet Page 12 (p12_fig01)
Datasheet Page 12 (p12_fig01)
P45 · p45_fig011828×2291px
ESP32-S2R2 (VFQFN-56-EP) — 附录A - ESP32-S2 系列芯片管脚清单
附录A - ESP32-S2 系列芯片管脚清单
P52 · p52_fig011754×749px
ESP32-S2R2 (VFQFN-56-EP) — www.espressif.com | 免责声明和版权公告 | 本文档中的信息，包括供参考的URL 地址，如有变更，恕不另行通知。 | 本文档可能引用了第三方的信息，所有引用的信息均为“按现状”提供，乐鑫不对信 息的准确性、真实性做任何保证。 | 乐鑫不对本文档的内容做任何保证，包括内容的适销性、是否适用于特定用途，也不 提供任何其他乐鑫提案、规格书或样品在他处提到的任何保证。 | 乐鑫不对本文档是否侵犯第三方权利做任何保证，也不对使用本文档内信息导致的任 何侵犯知识产权的行
www.espressif.com | 免责声明和版权公告 | 本文档中的信息，包括供参考的URL 地址，如有变更，恕不另行通知。 | 本文档可能引用了第三方的信息，所有引用的信息均为“按现状”提供，乐鑫不对信 息的准确性、真实性做任何保证。 | 乐鑫不对本文档的内容做任何保证，包括内容的适销性、是否适用于特定用途，也不 提供任何其他乐鑫提案、规格书或样品在他处提到的任何保证。 | 乐鑫不对本文档是否侵犯第三方权利做任何保证，也不对使用本文档内信息导致的任 何侵犯知识产权的行

Technical Specifications & Part Details (ESP32-S2R2)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ESP32-S2R2 (VFQFN-56-EP) is a 56-pin wireless wi-fi / bluetooth le soc module featuring a 7.00 × 7.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG, TOUCH interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
500 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (VFQFN-56-EP)
Pin Count & Lead PitchN / e
56 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG, TOUCH
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (GPIO0, MTDO, MTDI): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol57 auto-grouped pins
OK
IPC-7351B Land Pattern57 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 4.00×4.00mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VFQFN-56-EP)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.85 mm
Pins / Total PadsTopology
57P / 57Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2
BOM
22µF (or 10µF) X5R + 100nF X7R
0805 + 0402
3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA.
R_en + C_en
BOM
R = 10kΩ to 3V3 + C = 1µF to GND
0402 / 0603
Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot.
R_boot + SW1
BOM
10kΩ Pull-up + BOOT button
0402 + SMD
Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download.
D_esd
BOM
USBLC6-2SC6 / LESD5D5.0CT1G
SOT-23-6 / SOD-523
ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20.
ESP32-S3-MINI-1-N8 / 1U-N4R2
Espressif
100% Drop-inSame 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping.

Technical Frequently Asked Questions (FAQ) — ESP32-S2R2 (VFQFN-56-EP)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP32-S2R2 (VFQFN-56-EP)?

Manufactured by ESPRESSIF, the ESP32-S2R2 is housed in a VFQFN-56-EP package with 57 pins and a 0.40 mm lead pitch. Key pins include: 1 (VDDA: Power Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))), 2 (LNA_IN: Multiplexed I/O & Peripheral Pin LNA_IN (General)), 3 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 4 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 5 (GPIO0: Multiplexed I/O & Peripheral Pin GPIO0 (RTC/CLK)), 6 (GPIO1: Multiplexed I/O & Peripheral Pin GPIO1 (RTC/CLK, TOUCH)).

What are the IPC-7351B PCB Footprint dimensions for ESP32-S2R2?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-S2R2 (VFQFN-56-EP) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.40 mm, and 57 copper pads plus a central exposed thermal pad (EPAD) of 4.00 × 4.00 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-S2R2?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-S2R2 (ESPRESSIF, VFQFN-56-EP) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (57 pins) & ESP32-S2 / ESP32-S2FH2 / ESP32-S2FH4 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
2LNA_INRF_50OhmSignal terminal LNA_IN (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: LNA_IN. Supported peripheral buses: General.
3VDD3P3Power_InPrimary positive power supply input (VDD3P3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
4VDD3P3Power_InPrimary positive power supply input (VDD3P3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
5GPIO0Digital_IOSignal terminal GPIO0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO0. Supported peripheral buses: RTC/CLK.
6GPIO1Digital_IOSignal terminal GPIO1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO1. Supported peripheral buses: RTC/CLK, TOUCH.
7GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO2. Supported peripheral buses: RTC/CLK, TOUCH.
8GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO3. Supported peripheral buses: RTC/CLK, TOUCH.
9GPIO4Digital_IOSignal terminal GPIO4 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO4. Supported peripheral buses: RTC/CLK, TOUCH.
10GPIO5Digital_IOSignal terminal GPIO5 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO5. Supported peripheral buses: RTC/CLK, TOUCH.
11GPIO6Digital_IOSignal terminal GPIO6 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO6. Supported peripheral buses: RTC/CLK, TOUCH.
12GPIO7Digital_IOSignal terminal GPIO7 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO7. Supported peripheral buses: RTC/CLK, TOUCH.
13GPIO8Digital_IOSignal terminal GPIO8 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO8. Supported peripheral buses: RTC/CLK, TOUCH.
14GPIO9Digital_IOSignal terminal GPIO9 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO9. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
15GPIO10Digital_IOSignal terminal GPIO10 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO10, TOUCH10. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
16GPIO11Digital_IOSignal terminal GPIO11 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO11, TOUCH11. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
17GPIO12Digital_IOSignal terminal GPIO12 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO12, TOUCH12. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
18GPIO13Digital_IOSignal terminal GPIO13 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO13, TOUCH13. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
19GPIO14Digital_IOSignal terminal GPIO14 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO14, TOUCH14. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
20VDD3P3_RTCPower_InPrimary positive power supply input (VDD3P3_RTC) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
21XTAL_32KP_Digital_IOSignal terminal XTAL_32KP_ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO15, GPIO15, U0RTS. Supported peripheral buses: ADC, RTC/CLK.
22XTAL_32KN_Digital_IOSignal terminal XTAL_32KN_ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO16, GPIO16, U0CTS. Supported peripheral buses: ADC, RTC/CLK.
23DAC_1AnalogSignal terminal DAC_1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO17, GPIO17, U1TXD. Supported peripheral buses: UART, ADC, DAC, RTC/CLK.
24DAC_2AnalogSignal terminal DAC_2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7. Supported peripheral buses: UART, ADC, DAC, RTC/CLK.
25GPIO19Digital_IOSignal terminal GPIO19 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO19, U1RTS, ADC2_CH8. Supported peripheral buses: ADC, RTC/CLK.
26GPIO20Digital_IOSignal terminal GPIO20 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO20, U1CTS, ADC2_CH9, CLK_OUT1. Supported peripheral buses: USB, ADC, RTC/CLK.
27VDD3P3_RTCIO_Power_InPrimary positive power supply input (VDD3P3_RTCIO_) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
28GPIO21Digital_IOSignal terminal GPIO21 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO21. Supported peripheral buses: RTC/CLK.
29SPICS1Digital_IOSignal terminal SPICS1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO26. Supported peripheral buses: SPI.
30VDD_SPIPower_OutRegulated power output rail (VDD_SPI) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
31SPIHDDigital_IOSignal terminal SPIHD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO27. Supported peripheral buses: SPI.
32SPIWPDigital_IOSignal terminal SPIWP (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO28. Supported peripheral buses: SPI.
33SPICS0Digital_IOSignal terminal SPICS0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO29. Supported peripheral buses: SPI.
34SPICLKDigital_IOSignal terminal SPICLK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO30. Supported peripheral buses: SPI.
35SPIQDigital_IOSignal terminal SPIQ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO31. Supported peripheral buses: SPI.
36SPIDDigital_IOSignal terminal SPID (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO32. Supported peripheral buses: SPI.
37GPIO33Digital_IOSignal terminal GPIO33 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIIO4, FSPIHD. Supported peripheral buses: SPI.
38GPIO34Digital_IOSignal terminal GPIO34 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIIO5, FSPICS0. Supported peripheral buses: SPI.
39GPIO35Digital_IOSignal terminal GPIO35 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIIO6, FSPID. Supported peripheral buses: SPI.
40GPIO36Digital_IOSignal terminal GPIO36 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIIO7, FSPICLK. Supported peripheral buses: SPI.
41GPIO37Digital_IOSignal terminal GPIO37 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIDQS, FSPIQ. Supported peripheral buses: SPI.
42GPIO38Digital_IOSignal terminal GPIO38 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: FSPIWP. Supported peripheral buses: SPI.
43MTCKDigital_IOSignal terminal MTCK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO39, CLK_OUT3. Supported peripheral buses: SWD/JTAG.
44MTDODigital_IOSignal terminal MTDO (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO40, CLK_OUT2. Supported peripheral buses: SWD/JTAG.
45VDD3P3_CPUPower_InPrimary positive power supply input (VDD3P3_CPU) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
46MTDIDigital_IOSignal terminal MTDI (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO41, CLK_OUT1. Supported peripheral buses: SWD/JTAG.
47MTMSDigital_IOSignal terminal MTMS (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO42. Supported peripheral buses: SWD/JTAG.
48U0TXDDigital_IOSignal terminal U0TXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO43, CLK_OUT1. Supported peripheral buses: UART.
49U0RXDDigital_IOSignal terminal U0RXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO44, CLK_OUT2. Supported peripheral buses: UART.
50GPIO45Digital_IOSignal terminal GPIO45 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO45. Supported peripheral buses: General.
51VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
52XTAL_NDigital_IOSignal terminal XTAL_N (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_N. Supported peripheral buses: RTC/CLK.
53XTAL_PDigital_IOSignal terminal XTAL_P (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_P. Supported peripheral buses: RTC/CLK.
54VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
55GPIO46Digital_IOSignal terminal GPIO46 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO46. Supported peripheral buses: General.
56CHIP_PUDigital_IOChip enable and power-on reset control input (CHIP_PU): High enables the SoC; Low powers down the chip into reset.
57GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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