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CH32V203C8T6 (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32V203C8T6

WCHID: C3001172LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32V203C8T6 (LQFP-48(7x7))1VBAT2PC13 - TAMPE33V34PC15 - OSC325OSC IN(4)_6OSC OUT(4)_7NRST8VSSA9PC110PC211PC312VSSA13VDDA14PA0 WKUP -15PA116PA217PA318VSS_419VDD_IO4_20PA421PA522PA623PA724PC448VDD_VIO_347VSS_346PA1345PA1244PA1143PA1042PA941PA840PC939PC838PC737PC636PB1535PB1434PB1333PB1232VDD_IO1_31VSS_130PB1129PB1028PB227PB126PB025PC5Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.835.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
2PC13 - TAMPER -I/OMultiplexed I/O & Peripheral Pin PC13 - TAMPER - (RTC/CLK)
33V3Power3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4PC15 - OSC32 OUT(2)_I/OMultiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(2)_ (RTC/CLK)
5OSC IN(4)_I/OMultiplexed I/O & Peripheral Pin OSC IN(4)_ (RTC/CLK)
6OSC OUT(4)_I/OMultiplexed I/O & Peripheral Pin OSC OUT(4)_ (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8VSSAGNDGround Reference Pin (VSSA)
9PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
10PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
11PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
12VSSAGNDGround Reference Pin (VSSA)
13VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
14PA0 WKUP -I/OMultiplexed I/O & Peripheral Pin PA0 WKUP - (UART, ADC)
15PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
16PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
17PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
18VSS_4GNDGround Reference Pin (VSS_4)
19VDD_IO4_PowerPower Supply Input (VDD_IO4_ — 3.3V / 5.0V Standard Logic)
20PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI)
21PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
22PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
23PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
24PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
25PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
26PB0I/OMultiplexed I/O & Peripheral Pin PB0 (PWM)
27PB1I/OMultiplexed I/O & Peripheral Pin PB1 (PWM)
28PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
29PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
30PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
31VSS_1GNDGround Reference Pin (VSS_1)
32VDD_IO1_PowerPower Supply Input (VDD_IO1_ — 3.3V / 5.0V Standard Logic)
33PB12I/OMultiplexed I/O & Peripheral Pin PB12 (SPI, I2C)
34PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
35PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
36PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM)
37PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
38PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
39PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
40PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
41PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
42PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, PWM)
43PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, PWM)
44PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART)
45PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART)
46PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
47VSS_3GNDGround Reference Pin (VSS_3)
48VDD_VIO_3PowerPower Supply Input (VDD_VIO_3 — 3.3V / 5.0V Standard Logic)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
Design note: VBAT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32V203C8T6 (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32V203C8T6 (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32V203C8T6 (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32V203C8T6 (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32V203C8T6 (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32V203C8T6 (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32V203C8T6 (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for CH32V203
P26 · p26_fig01EXACT PACKAGE
CH32V203C8T6 (LQFP-48(7x7)) — Table 3-1-2 TSSOP20(F8)/QSOP28(G8) pin definitions
Table 3-1-2 TSSOP20(F8)/QSOP28(G8) pin definitions
P62 · p62_fig01EXACT PACKAGE
CH32V203C8T6 (LQFP-48(7x7)) — Figure 5-6 LQFP48 package
Figure 5-6 LQFP48 package
P1 · p01_fig01246×131px
CH32V203C8T6 (LQFP-48(7x7)) — Overview
Overview
P21 · p21_fig011703×2016px
CH32V203C8T6 (LQFP-48(7x7)) — CH32V203 Datasheet http://wch-ic.com
CH32V203 Datasheet http://wch-ic.com
P21 · p21_fig01P21
CH32V203C8T6 (LQFP-48(7x7)) — Datasheet Page 21 (p21_fig01)
Datasheet Page 21 (p21_fig01)
P26 · p26_fig021843×1231px
CH32V203C8T6 (LQFP-48(7x7)) — V2.8 6
V2.8 6
P26 · p26_fig01P26
CH32V203C8T6 (LQFP-48(7x7)) — Datasheet Page 26 (p26_fig01)
Datasheet Page 26 (p26_fig01)
P41 · p41_fig01462×510px
CH32V203C8T6 (LQFP-48(7x7)) — Figure 4-2 Current consumption measurement
Figure 4-2 Current consumption measurement
P55 · p55_fig011852×1111px
CH32V203C8T6 (LQFP-48(7x7)) — Table 4-28 Maximum RAIN when fADC = 14MHz | TS(cycle) tS (us) Maximum RAIN(kΩ) | 1.5 0.11 0.4 | 7.5 0.54 5.9 | 13.5 0.96 11.4 | 28.5 2.04 25.2 | 41.5 2.96 37.2 | 55.5 3.96 50 | 71.5 5.11 Invalid | 239.5 17.1 Invalid | Table 4-29 ADC error |
Table 4-28 Maximum RAIN when fADC = 14MHz | TS(cycle) tS (us) Maximum RAIN(kΩ) | 1.5 0.11 0.4 | 7.5 0.54 5.9 | 13.5 0.96 11.4 | 28.5 2.04 25.2 | 41.5 2.96 37.2 | 55.5 3.96 50 | 71.5 5.11 Invalid | 239.5 17.1 Invalid | Table 4-29 ADC error |
P55 · p55_fig01P55
CH32V203C8T6 (LQFP-48(7x7)) — Datasheet Page 55 (p55_fig01)
Datasheet Page 55 (p55_fig01)
P62 · p62_fig021269×921px
CH32V203C8T6 (LQFP-48(7x7)) — Figure 5-7 LQFP64M package
Figure 5-7 LQFP64M package
P63 · p63_fig011145×1437px
CH32V203C8T6 (LQFP-48(7x7)) — Figure 5-8 QSOP28 package
Figure 5-8 QSOP28 package
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (CH32V203C8T6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:CH32V203C8T6 (LQFP-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
144MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
17 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32V203C8T6 (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32V203C8T6 (LQFP-48(7x7))?

Manufactured by WCH, the CH32V203C8T6 is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)), 2 (PC13 - TAMPER -: Multiplexed I/O & Peripheral Pin PC13 - TAMPER - (RTC/CLK)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (PC15 - OSC32 OUT(2)_: Multiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(2)_ (RTC/CLK)), 5 (OSC IN(4)_: Multiplexed I/O & Peripheral Pin OSC IN(4)_ (RTC/CLK)), 6 (OSC OUT(4)_: Multiplexed I/O & Peripheral Pin OSC OUT(4)_ (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH32V203C8T6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V203C8T6 (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V203C8T6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V203C8T6 (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH32V203 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2PC13 - TAMPER -Digital_IOSignal terminal PC13 - TAMPER - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13 - TAMPER -. Supported peripheral buses: RTC/CLK.
33V3Power_In3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4PC15 - OSC32 OUT(2)_Digital_IOSignal terminal PC15 - OSC32 OUT(2)_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15 - OSC32 OUT(2)_. Supported peripheral buses: RTC/CLK.
5OSC IN(4)_Digital_IOSignal terminal OSC IN(4)_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC IN(4)_. Supported peripheral buses: RTC/CLK.
6OSC OUT(4)_Digital_IOSignal terminal OSC OUT(4)_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC OUT(4)_. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
9PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
10PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
11PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
12VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
13VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14PA0 WKUP -Digital_IOSignal terminal PA0 WKUP - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0 WKUP -. Supported peripheral buses: UART, ADC.
15PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
16PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
17PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
18VSS_4GND0V electrical ground return terminal (VSS_4) for internal core logic, I/O drivers, and analog sub-blocks.
19VDD_IO4_Power_InPrimary positive power supply input (VDD_IO4_) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI.
21PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC.
22PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC, PWM.
23PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
24PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
25PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
26PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: PWM.
27PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: PWM.
28PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
29PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C.
30PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, I2C.
31VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
32VDD_IO1_Power_InPrimary positive power supply input (VDD_IO1_) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
33PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA. Supported peripheral buses: SPI, I2C.
34PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
35PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, PWM.
36PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, PWM.
37PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
38PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
39PC8Digital_IOSignal terminal PC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
40PC9Digital_IOSignal terminal PC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
41PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, PWM, RTC/CLK.
42PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM.
43PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, PWM.
44PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: USB, UART.
45PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART.
46PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
47VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
48VDD_VIO_3Power_InPrimary positive power supply input (VDD_VIO_3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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