ChipDocs.org
⌘K
2284 PARTSUpload PDF
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP32-S3-WROOM-1U-N8

ESPRESSIFID: C2980297SMD,19.2x18mm · 41 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm)1GND23V33EN4IO45IO56IO67IO78IO159IO1610IO1711IO1812IO813IO1914IO2015IO316IO4617IO918IO1019IO1120IO1221IO1341EPAD40GND39IO138IO237TXD036RXD035IO4234IO4133IO4032IO3931IO3830IO37b29IO36b28IO35b27IO026IO4525IO48c24IO47c23IO2122IO14Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.833.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414141414141414141E=18.00mm · Pitch e=1.27mmD=19.20mm-15-13-11-9-7-5-3-11357911131515131197531-1-3-5-7-9-11-13-15mm
3. 3D CAD MODEL
Package Body: 18.00mm × 19.20mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (41/41)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GNDGNDGround Reference Pin (GND)
23V3PowerPower Supply Input (3V3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
3ENISystem Enable & Hardware Reset (EN)
4IO4I/OMultiplexed I/O & Peripheral Pin IO4 (RTC/CLK, TOUCH)
5IO5I/OMultiplexed I/O & Peripheral Pin IO5 (RTC/CLK, TOUCH)
6IO6I/OMultiplexed I/O & Peripheral Pin IO6 (RTC/CLK, TOUCH)
7IO7I/OMultiplexed I/O & Peripheral Pin IO7 (RTC/CLK, TOUCH)
8IO15I/OMultiplexed I/O & Peripheral Pin IO15 (ADC, RTC/CLK)
9IO16I/OMultiplexed I/O & Peripheral Pin IO16 (ADC, RTC/CLK)
10IO17I/OMultiplexed I/O & Peripheral Pin IO17 (UART, RTC/CLK)
11IO18I/OMultiplexed I/O & Peripheral Pin IO18 (UART, ADC, RTC/CLK)
12IO8I/OMultiplexed I/O & Peripheral Pin IO8 (ADC, RTC/CLK, TOUCH)
13IO19I/OMultiplexed I/O & Peripheral Pin IO19 (ADC, RTC/CLK)
14IO20I/OMultiplexed I/O & Peripheral Pin IO20 (USB, ADC, RTC/CLK)
15IO3I/OMultiplexed I/O & Peripheral Pin IO3 (RTC/CLK, TOUCH)
16IO46I/OMultiplexed I/O & Peripheral Pin IO46 (General)
17IO9I/OMultiplexed I/O & Peripheral Pin IO9 (ADC, RTC/CLK, TOUCH)
18IO10I/OMultiplexed I/O & Peripheral Pin IO10 (SPI, ADC, RTC/CLK, TOUCH)
19IO11I/OMultiplexed I/O & Peripheral Pin IO11 (SPI, ADC, RTC/CLK, TOUCH)
20IO12I/OMultiplexed I/O & Peripheral Pin IO12 (SPI, ADC, RTC/CLK, TOUCH)
21IO13I/OMultiplexed I/O & Peripheral Pin IO13 (SPI, ADC, RTC/CLK, TOUCH)
22IO14I/OMultiplexed I/O & Peripheral Pin IO14 (SPI, ADC, RTC/CLK, TOUCH)
23IO21I/OMultiplexed I/O & Peripheral Pin IO21 (RTC/CLK)
24IO47cI/OMultiplexed I/O & Peripheral Pin IO47c (SPI)
25IO48cI/OMultiplexed I/O & Peripheral Pin IO48c (SPI)
26IO45I/OMultiplexed I/O & Peripheral Pin IO45 (General)
27IO0I/OMultiplexed I/O & Peripheral Pin IO0 (RTC/CLK)
28IO35bI/OMultiplexed I/O & Peripheral Pin IO35b (SPI)
29IO36bI/OMultiplexed I/O & Peripheral Pin IO36b (SPI)
30IO37bI/OMultiplexed I/O & Peripheral Pin IO37b (SPI)
31IO38IInput-Only Pin IO38 (SPI)
32IO39IInput-Only Pin IO39 (SPI, SWD/JTAG)
33IO40I/OMultiplexed I/O & Peripheral Pin IO40 (SWD/JTAG)
34IO41I/OMultiplexed I/O & Peripheral Pin IO41 (SWD/JTAG)
35IO42I/OMultiplexed I/O & Peripheral Pin IO42 (SWD/JTAG)
36RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
37TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
38IO2I/OMultiplexed I/O & Peripheral Pin IO2 (RTC/CLK, TOUCH)
39IO1I/OMultiplexed I/O & Peripheral Pin IO1 (RTC/CLK, TOUCH)
40GNDGNDGround Reference Pin (GND)
41EPADGNDExposed Thermal & Ground Pad (EPAD)
PIN 1 GND
GND
Ground Reference Pin (GND)
Design note: 接地
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP32-S3-WROOM-1U-N8 (ESPRESSIF · SMD,19.2x18mm)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) - 2. Standard Pinout (Top View)
True package pinout (41 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) - 4. Package Dimensions (D×E×A)
SMD,19.2x18mm · 18.00×19.20mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)
Showing 1–12 of 17 uncropped original figures for ESP32-S3-WROOM
P1 · p01_fig01EXACT PACKAGE
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — ESP32-S3-WROOM-1 ESP32-S3-WROOM-1U
ESP32-S3-WROOM-1 ESP32-S3-WROOM-1U
P1 · p01_fig02EXACT PACKAGE
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — ESP32-S3-WROOM-1 ESP32-S3-WROOM-1U
ESP32-S3-WROOM-1 ESP32-S3-WROOM-1U
P27 · p27_fig01EXACT PACKAGE
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — 图6: ESP32-S3-WROOM-1U 原理图
图6: ESP32-S3-WROOM-1U 原理图
P27 · p27_fig02EXACT PACKAGE
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — 图6: ESP32-S3-WROOM-1U 原理图
图6: ESP32-S3-WROOM-1U 原理图
P27 · p27_fig03EXACT PACKAGE
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — 图6: ESP32-S3-WROOM-1U 原理图
图6: ESP32-S3-WROOM-1U 原理图
P28 · p28_fig01EXACT PACKAGE
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — 图7: 外围设计原理图
图7: 外围设计原理图
P31 · p31_fig01EXACT PACKAGE
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — 图11: ESP32-S3-WROOM-1U 推荐PCB 封装图
图11: ESP32-S3-WROOM-1U 推荐PCB 封装图
P1 · p01_fig03646×314px
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — www.espressif.com
www.espressif.com
P1 · p01_fig01P1
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P10 · p10_fig011306×1221px
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — 图3: 管脚布局（顶视图）
图3: 管脚布局（顶视图）
P10 · p10_fig01P10
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — Datasheet Page 10 (p10_fig01)
Datasheet Page 10 (p10_fig01)
P27 · p27_fig041461×1261px
ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) — 50 ohm Impedance Control
50 ohm Impedance Control
Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (ESP32-S3-WROOM-1U-N8)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) is a 41-pin wireless wi-fi / bluetooth le soc module featuring a 19.20 × 18.00 × 3.20 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 3.0 ~ 3.6 V supply operation across 65 °C – 85 °C with integrated Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, RTC/CLK, SWD/JTAG, TOUCH interfaces.
Operating Supply VoltageV_CC / V_DD
3.0 ~ 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
65 °C – 85 °C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_TX(peak) ≈ 310 mA @ 3.3V | Deep-Sleep ≈ 10 µA | I_GPIO(max) = 40 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
19.20 × 18.00 × 3.20 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (SMD,19.2x18mm)
Pin Count & Lead PitchN / e
41 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, RTC/CLK, SWD/JTAG, TOUCH
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (IO46, IO45, IO0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol41 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteEPAD 3.70×3.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SMD,19.2x18mm)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
19.20 × 18.00 mm
Height (A) & Pitch (e)IPC-7351B
A=3.20mm · e=1.27mm
Pad Size (W × L)Level B
0.90 × 1.50 mm
Pins / Total PadsTopology
41P / 49Pad (CASTELLATED_MODULE)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2
BOM
22µF (or 10µF) X5R + 100nF X7R
0805 + 0402
3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA.
R_en + C_en
BOM
R = 10kΩ to 3V3 + C = 1µF to GND
0402 / 0603
Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot.
R_boot + SW1
BOM
10kΩ Pull-up + BOOT button
0402 + SMD
Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download.
D_esd
BOM
USBLC6-2SC6 / LESD5D5.0CT1G
SOT-23-6 / SOD-523
ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20.
ESP32-S3-MINI-1-N8 / 1U-N4R2
Espressif
100% Drop-inSame 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping.

Technical Frequently Asked Questions (FAQ) — ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm)?

Manufactured by ESPRESSIF, the ESP32-S3-WROOM-1U-N8 is housed in a SMD,19.2x18mm package with 41 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 3.0 ~ 3.6 V. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (3V3: Power Supply Input (3V3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 3 (EN: System Enable & Hardware Reset (EN)), 4 (IO4: Multiplexed I/O & Peripheral Pin IO4 (RTC/CLK, TOUCH)), 5 (IO5: Multiplexed I/O & Peripheral Pin IO5 (RTC/CLK, TOUCH)), 6 (IO6: Multiplexed I/O & Peripheral Pin IO6 (RTC/CLK, TOUCH)).

What are the IPC-7351B PCB Footprint dimensions for ESP32-S3-WROOM-1U-N8?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-S3-WROOM-1U-N8 (SMD,19.2x18mm) has a nominal body envelope of 18.00 × 19.20 mm, pitch e = 1.27 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 3.70 × 3.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-S3-WROOM-1U-N8?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-S3-WROOM-1U-N8 (ESPRESSIF, SMD,19.2x18mm) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (41 pins) & ESP32-S3-WROOM Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
23V3Power_InPrimary positive power supply input (3V3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
3ENDigital_IOChip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
4IO4Digital_IOSignal terminal IO4 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO4. Supported peripheral buses: RTC/CLK, TOUCH.
5IO5Digital_IOSignal terminal IO5 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO5. Supported peripheral buses: RTC/CLK, TOUCH.
6IO6Digital_IOSignal terminal IO6 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO6. Supported peripheral buses: RTC/CLK, TOUCH.
7IO7Digital_IOSignal terminal IO7 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO7. Supported peripheral buses: RTC/CLK, TOUCH.
8IO15Digital_IOSignal terminal IO15 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO15, GPIO15, U0RTS. Supported peripheral buses: ADC, RTC/CLK.
9IO16Digital_IOSignal terminal IO16 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO16, GPIO16, U0CTS. Supported peripheral buses: ADC, RTC/CLK.
10IO17Digital_IOSignal terminal IO17 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO17. Supported peripheral buses: UART, RTC/CLK.
11IO18Digital_IOSignal terminal IO18 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO18, GPIO18, U1RXD. Supported peripheral buses: UART, ADC, RTC/CLK.
12IO8Digital_IOSignal terminal IO8 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO8, GPIO8. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
13IO19Digital_IOSignal terminal IO19 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8. Supported peripheral buses: ADC, RTC/CLK.
14IO20Digital_IOSignal terminal IO20 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1. Supported peripheral buses: USB, ADC, RTC/CLK.
15IO3Digital_IOSignal terminal IO3 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO3. Supported peripheral buses: RTC/CLK, TOUCH.
16IO46Digital_IOSignal terminal IO46 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO46. Supported peripheral buses: General.
17IO9Digital_IOSignal terminal IO9 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO9, GPIO9, TOUCH9. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
18IO10Digital_IOSignal terminal IO10 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO10, GPIO10, TOUCH10, SUBSPICS0. Supported peripheral buses: SPI, ADC, RTC/CLK, TOUCH.
19IO11Digital_IOSignal terminal IO11 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO11, GPIO11, TOUCH11, SUBSPID. Supported peripheral buses: SPI, ADC, RTC/CLK, TOUCH.
20IO12Digital_IOSignal terminal IO12 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO12, GPIO12, TOUCH12, SUBSPICLK. Supported peripheral buses: SPI, ADC, RTC/CLK, TOUCH.
21IO13Digital_IOSignal terminal IO13 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO13, GPIO13, TOUCH13, SUBSPIQ. Supported peripheral buses: SPI, ADC, RTC/CLK, TOUCH.
22IO14Digital_IOSignal terminal IO14 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO14, GPIO14, TOUCH14, SUBSPIWP. Supported peripheral buses: SPI, ADC, RTC/CLK, TOUCH.
23IO21Digital_IOSignal terminal IO21 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: IO21. Supported peripheral buses: RTC/CLK.
24IO47cDigital_IOSignal terminal IO47c (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPICLK. Supported peripheral buses: SPI.
25IO48cDigital_IOSignal terminal IO48c (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPICLK. Supported peripheral buses: SPI.
26IO45Digital_IOSignal terminal IO45 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO45. Supported peripheral buses: General.
27IO0Digital_IOSignal terminal IO0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: IO0. Supported peripheral buses: RTC/CLK.
28IO35bDigital_IOSignal terminal IO35b (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIIO6, GPIO35, FSPID, SUBSPID. Supported peripheral buses: SPI.
29IO36bDigital_IOSignal terminal IO36b (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIIO7, GPIO36, FSPICLK, SUBSPICLK. Supported peripheral buses: SPI.
30IO37bDigital_IOSignal terminal IO37b (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIDQS, GPIO37, FSPIQ, SUBSPIQ. Supported peripheral buses: SPI.
31IO38Digital_IOSignal terminal IO38 (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO38, FSPIWP, SUBSPIWP. Supported peripheral buses: SPI.
32IO39Digital_IOSignal terminal IO39 (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTCK, GPIO39, CLK_OUT3, SUBSPICS1. Supported peripheral buses: SPI, SWD/JTAG.
33IO40Digital_IOSignal terminal IO40 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDO, GPIO40, CLK_OUT2. Supported peripheral buses: SWD/JTAG.
34IO41Digital_IOSignal terminal IO41 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDI, GPIO41, CLK_OUT1. Supported peripheral buses: SWD/JTAG.
35IO42Digital_IOSignal terminal IO42 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTMS, GPIO42. Supported peripheral buses: SWD/JTAG.
36RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0RXD, GPIO44, CLK_OUT2. Supported peripheral buses: UART.
37TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0TXD, GPIO43, CLK_OUT1. Supported peripheral buses: UART.
38IO2Digital_IOSignal terminal IO2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO2. Supported peripheral buses: RTC/CLK, TOUCH.
39IO1Digital_IOSignal terminal IO1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: RTC_GPIO1. Supported peripheral buses: RTC/CLK, TOUCH.
40GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
41EPADGNDBottom exposed die attach pad (EPAD) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
ExplorePartsPackagesMFRsUpload