ChipDocs.org
⌘K
2284 PARTSUpload PDF
C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6) — Symbol, Footprint IPC-7351B & 3D STEP Model

C2980295

SemiconductorQFN-56_L7.0-W7.0-P0.40-TL-EP4.6 · 57 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6)1LNA_IN2VDD3P33VDD3P34CHIP_PU5GPIO06GPIO17GPIO28GPIO39GPIO410GPIO511GPIO612GPIO713GPIO814GPIO915GPIO1016GPIO1117GPIO1218GPIO1319GPIO1420VDD3P3_RTC21XTAL_32K_P22XTAL_32K_N23GPIO1724GPIO1825GPIO1926GPIO2027GPIO2128SPCS129VDD_SPI57PAD56VDDA55VDDA54XTAL_P53XTAL_N52GPIO4651GPIO4550U0RXD49U0TXD48MTMS47MTDI46VDD3P3_CPU45MTDO44MTCK43GPIO3842GPIO3741GPIO3640GPIO3539GPIO3438GPIO3337SPICLK_P36SPICLK_N35SPID34SPIQ33SPICLK32SPICS031SPIWP30SPIHDGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.243.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657E=7.00mm · Pitch e=0.40mmD=7.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (57/57)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1LNA_INI/OMultiplexed I/O & Peripheral Pin LNA_IN (General)
2VDD3P3PowerPower Supply Input (VDD3P3 — 3.3V / 5.0V Standard Logic)
3VDD3P3PowerPower Supply Input (VDD3P3 — 3.3V / 5.0V Standard Logic)
4CHIP_PUISystem Enable & Hardware Reset (CHIP_PU)
5GPIO0I/OMultiplexed I/O & Peripheral Pin GPIO0 (General)
6GPIO1I/OMultiplexed I/O & Peripheral Pin GPIO1 (General)
7GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (General)
8GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (General)
9GPIO4I/OMultiplexed I/O & Peripheral Pin GPIO4 (General)
10GPIO5I/OMultiplexed I/O & Peripheral Pin GPIO5 (General)
11GPIO6I/OMultiplexed I/O & Peripheral Pin GPIO6 (General)
12GPIO7I/OMultiplexed I/O & Peripheral Pin GPIO7 (General)
13GPIO8I/OMultiplexed I/O & Peripheral Pin GPIO8 (General)
14GPIO9I/OMultiplexed I/O & Peripheral Pin GPIO9 (General)
15GPIO10I/OMultiplexed I/O & Peripheral Pin GPIO10 (General)
16GPIO11I/OMultiplexed I/O & Peripheral Pin GPIO11 (General)
17GPIO12I/OMultiplexed I/O & Peripheral Pin GPIO12 (General)
18GPIO13I/OMultiplexed I/O & Peripheral Pin GPIO13 (General)
19GPIO14I/OMultiplexed I/O & Peripheral Pin GPIO14 (General)
20VDD3P3_RTCPowerPower Supply Input (VDD3P3_RTC — 3.3V / 5.0V Standard Logic)
21XTAL_32K_PI/OMultiplexed I/O & Peripheral Pin XTAL_32K_P (RTC/CLK)
22XTAL_32K_NI/OMultiplexed I/O & Peripheral Pin XTAL_32K_N (RTC/CLK)
23GPIO17I/OMultiplexed I/O & Peripheral Pin GPIO17 (General)
24GPIO18I/OMultiplexed I/O & Peripheral Pin GPIO18 (General)
25GPIO19I/OMultiplexed I/O & Peripheral Pin GPIO19 (General)
26GPIO20I/OMultiplexed I/O & Peripheral Pin GPIO20 (General)
27GPIO21I/OMultiplexed I/O & Peripheral Pin GPIO21 (General)
28SPCS1I/OMultiplexed I/O & Peripheral Pin SPCS1 (General)
29VDD_SPIPowerPower Supply Input (VDD_SPI — 3.3V / 5.0V Standard Logic)
30SPIHDI/OMultiplexed I/O & Peripheral Pin SPIHD (SPI)
31SPIWPI/OMultiplexed I/O & Peripheral Pin SPIWP (SPI)
32SPICS0I/OMultiplexed I/O & Peripheral Pin SPICS0 (SPI)
33SPICLKI/OMultiplexed I/O & Peripheral Pin SPICLK (SPI)
34SPIQI/OMultiplexed I/O & Peripheral Pin SPIQ (SPI)
35SPIDI/OMultiplexed I/O & Peripheral Pin SPID (SPI)
36SPICLK_NI/OMultiplexed I/O & Peripheral Pin SPICLK_N (SPI)
37SPICLK_PI/OMultiplexed I/O & Peripheral Pin SPICLK_P (SPI)
38GPIO33I/OMultiplexed I/O & Peripheral Pin GPIO33 (General)
39GPIO34I/OMultiplexed I/O & Peripheral Pin GPIO34 (General)
40GPIO35I/OMultiplexed I/O & Peripheral Pin GPIO35 (General)
41GPIO36I/OMultiplexed I/O & Peripheral Pin GPIO36 (General)
42GPIO37I/OMultiplexed I/O & Peripheral Pin GPIO37 (General)
43GPIO38I/OMultiplexed I/O & Peripheral Pin GPIO38 (General)
44MTCKI/OMultiplexed I/O & Peripheral Pin MTCK (SWD/JTAG)
45MTDOI/OMultiplexed I/O & Peripheral Pin MTDO (SWD/JTAG)
46VDD3P3_CPUPowerPower Supply Input (VDD3P3_CPU — 3.3V / 5.0V Standard Logic)
47MTDII/OMultiplexed I/O & Peripheral Pin MTDI (SWD/JTAG)
48MTMSI/OMultiplexed I/O & Peripheral Pin MTMS (SWD/JTAG)
49U0TXDI/OMultiplexed I/O & Peripheral Pin U0TXD (UART)
50U0RXDI/OMultiplexed I/O & Peripheral Pin U0RXD (UART)
51GPIO45I/OMultiplexed I/O & Peripheral Pin GPIO45 (General)
52GPIO46I/OMultiplexed I/O & Peripheral Pin GPIO46 (General)
53XTAL_NI/OMultiplexed I/O & Peripheral Pin XTAL_N (RTC/CLK)
54XTAL_PI/OMultiplexed I/O & Peripheral Pin XTAL_P (RTC/CLK)
55VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
56VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
57PADI/OMultiplexed I/O & Peripheral Pin PAD (General)
PIN 1 LNA_IN
I/O
Multiplexed I/O & Peripheral Pin LNA_IN (General)
Design note: Signal terminal LNA_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LNA_IN. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C2980295 (Semiconductor · QFN-56_L7.0-W7.0-P0.40-TL-EP4.6)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6) - 2. Standard Pinout (Top View)
True package pinout (57 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6) - 4. Package Dimensions (D×E×A)
QFN-56_L7.0-W7.0-P0.40-TL-EP4.6 · 7.00×7.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6) - 5. Recommended Land Pattern
IPC-7351B Footprint (57 Pads)Expand ›
6. Application SchematicSCHEMATIC
C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C2980295)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6) is a 56-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK, SPI, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6)
Pin Count & Lead PitchN / e
56 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK, SPI, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol57 auto-grouped pins
OK
IPC-7351B Land Pattern57 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 3.20×3.20mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.85 mm
Pins / Total PadsTopology
57P / 57Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-56_L7.0-W7.0-P0.40-TL-EP4.6
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6)?

Manufactured by Semiconductor, the C2980295 is housed in a QFN-56_L7.0-W7.0-P0.40-TL-EP4.6 package with 57 pins and a 0.40 mm lead pitch. Key pins include: 1 (LNA_IN: Multiplexed I/O & Peripheral Pin LNA_IN (General)), 2 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V / 5.0V Standard Logic)), 3 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V / 5.0V Standard Logic)), 4 (CHIP_PU: System Enable & Hardware Reset (CHIP_PU)), 5 (GPIO0: Multiplexed I/O & Peripheral Pin GPIO0 (General)), 6 (GPIO1: Multiplexed I/O & Peripheral Pin GPIO1 (General)).

What are the IPC-7351B PCB Footprint dimensions for C2980295?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C2980295 (QFN-56_L7.0-W7.0-P0.40-TL-EP4.6) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.40 mm, and 57 copper pads plus a central exposed thermal pad (EPAD) of 3.20 × 3.20 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C2980295?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C2980295 (Semiconductor, QFN-56_L7.0-W7.0-P0.40-TL-EP4.6) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (57 pins) & ESP32-S3R2 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1LNA_INDigital_IOSignal terminal LNA_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LNA_IN. Supported peripheral buses: General.
2VDD3P3Power_InPrimary positive power supply input (VDD3P3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3VDD3P3Power_InPrimary positive power supply input (VDD3P3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4CHIP_PUDigital_IOChip enable and power-on reset control input (CHIP_PU): High enables the SoC; Low powers down the chip into reset.
5GPIO0Digital_IOSignal terminal GPIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO0. Supported peripheral buses: General.
6GPIO1Digital_IOSignal terminal GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: General.
7GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
8GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General.
9GPIO4Digital_IOSignal terminal GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO4. Supported peripheral buses: General.
10GPIO5Digital_IOSignal terminal GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO5. Supported peripheral buses: General.
11GPIO6Digital_IOSignal terminal GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO6. Supported peripheral buses: General.
12GPIO7Digital_IOSignal terminal GPIO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO7. Supported peripheral buses: General.
13GPIO8Digital_IOSignal terminal GPIO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General.
14GPIO9Digital_IOSignal terminal GPIO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General.
15GPIO10Digital_IOSignal terminal GPIO10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO10. Supported peripheral buses: General.
16GPIO11Digital_IOSignal terminal GPIO11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO11. Supported peripheral buses: General.
17GPIO12Digital_IOSignal terminal GPIO12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO12. Supported peripheral buses: General.
18GPIO13Digital_IOSignal terminal GPIO13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO13. Supported peripheral buses: General.
19GPIO14Digital_IOSignal terminal GPIO14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO14. Supported peripheral buses: General.
20VDD3P3_RTCPower_InPrimary positive power supply input (VDD3P3_RTC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21XTAL_32K_PDigital_IOSignal terminal XTAL_32K_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_32K_P. Supported peripheral buses: RTC/CLK.
22XTAL_32K_NDigital_IOSignal terminal XTAL_32K_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_32K_N. Supported peripheral buses: RTC/CLK.
23GPIO17Digital_IOSignal terminal GPIO17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO17. Supported peripheral buses: General.
24GPIO18Digital_IOSignal terminal GPIO18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO18. Supported peripheral buses: General.
25GPIO19Digital_IOSignal terminal GPIO19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO19. Supported peripheral buses: General.
26GPIO20Digital_IOSignal terminal GPIO20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO20. Supported peripheral buses: General.
27GPIO21Digital_IOSignal terminal GPIO21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO21. Supported peripheral buses: General.
28SPCS1Digital_IOSignal terminal SPCS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPCS1. Supported peripheral buses: General.
29VDD_SPIPower_InPrimary positive power supply input (VDD_SPI) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
30SPIHDDigital_IOSignal terminal SPIHD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPIHD. Supported peripheral buses: SPI.
31SPIWPDigital_IOSignal terminal SPIWP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPIWP. Supported peripheral buses: SPI.
32SPICS0Digital_IOSignal terminal SPICS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPICS0. Supported peripheral buses: SPI.
33SPICLKDigital_IOSignal terminal SPICLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPICLK. Supported peripheral buses: SPI.
34SPIQDigital_IOSignal terminal SPIQ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPIQ. Supported peripheral buses: SPI.
35SPIDDigital_IOSignal terminal SPID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPID. Supported peripheral buses: SPI.
36SPICLK_NDigital_IOSignal terminal SPICLK_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPICLK_N. Supported peripheral buses: SPI.
37SPICLK_PDigital_IOSignal terminal SPICLK_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPICLK_P. Supported peripheral buses: SPI.
38GPIO33Digital_IOSignal terminal GPIO33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO33. Supported peripheral buses: General.
39GPIO34Digital_IOSignal terminal GPIO34 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO34. Supported peripheral buses: General.
40GPIO35Digital_IOSignal terminal GPIO35 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO35. Supported peripheral buses: General.
41GPIO36Digital_IOSignal terminal GPIO36 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO36. Supported peripheral buses: General.
42GPIO37Digital_IOSignal terminal GPIO37 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO37. Supported peripheral buses: General.
43GPIO38Digital_IOSignal terminal GPIO38 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO38. Supported peripheral buses: General.
44MTCKDigital_IOSignal terminal MTCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MTCK. Supported peripheral buses: SWD/JTAG.
45MTDODigital_IOSignal terminal MTDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MTDO. Supported peripheral buses: SWD/JTAG.
46VDD3P3_CPUPower_InPrimary positive power supply input (VDD3P3_CPU) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
47MTDIDigital_IOSignal terminal MTDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MTDI. Supported peripheral buses: SWD/JTAG.
48MTMSDigital_IOSignal terminal MTMS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MTMS. Supported peripheral buses: SWD/JTAG.
49U0TXDDigital_IOSignal terminal U0TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: U0TXD. Supported peripheral buses: UART.
50U0RXDDigital_IOSignal terminal U0RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: U0RXD. Supported peripheral buses: UART.
51GPIO45Digital_IOSignal terminal GPIO45 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO45. Supported peripheral buses: General.
52GPIO46Digital_IOSignal terminal GPIO46 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO46. Supported peripheral buses: General.
53XTAL_NDigital_IOSignal terminal XTAL_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_N. Supported peripheral buses: RTC/CLK.
54XTAL_PDigital_IOSignal terminal XTAL_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_P. Supported peripheral buses: RTC/CLK.
55VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
56VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
57PADDigital_IOSignal terminal PAD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PAD. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload