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CH348Q (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH348Q

WCHID: C2979161LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH348Q (LQFP-48(7x7))1DCD5/ GPIO402RI5/ GPIO413DSR1/ GPIO274DCD1/ GPIO285RI1/ GPIO296XO7CFG8GND9NC10CTS1/GPIO211RTS1/GPIO312TXD113RXD114ACT15DTR1/ TNOW1/16TXD617RXD618TXD319RXD320GND21TXD222RXD223CTS1/ GPIO224RTS1/ GPIO348VCC47GND46RI3/ GPIO3545DCD3/ GPIO3444DSR3/ GPIO3343RI6/ GPIO4442DCD6/ GPIO4341DSR6/ GPIO4240RI7/ GPIO4739DCD7/ GPIO4638DSR7/ GPIO4537TXD736RTS7/ GPIO1935CTS7/ GPIO1834DTR0/ TNOW0/33RTS0/GPIO132RTS6/ GPIO1731CTS6/ GPIO1630TXD029ACT28RTS3/GPIO727RTS2/GPIO526CTS2/GPIO425CTS3/GPIO6Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DCD5/ GPIO40I/OMultiplexed I/O & Peripheral Pin DCD5/ GPIO40 (General)
2RI5/ GPIO41I/OMultiplexed I/O & Peripheral Pin RI5/ GPIO41 (General)
3DSR1/ GPIO27I/OMultiplexed I/O & Peripheral Pin DSR1/ GPIO27 (UART)
4DCD1/ GPIO28I/OMultiplexed I/O & Peripheral Pin DCD1/ GPIO28 (General)
5RI1/ GPIO29I/OMultiplexed I/O & Peripheral Pin RI1/ GPIO29 (General)
6XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
7CFGI/OMultiplexed I/O & Peripheral Pin CFG (General)
8GNDGNDGround Reference Pin (GND)
9NCI/OMultiplexed I/O & Peripheral Pin NC (General)
10CTS1/GPIO2I/OMultiplexed I/O & Peripheral Pin CTS1/GPIO2 (UART)
11RTS1/GPIO3I/OMultiplexed I/O & Peripheral Pin RTS1/GPIO3 (UART)
12TXD1I/OTXD1 (UART)
13RXD1I/ORXD1 (UART)
14ACTI/OMultiplexed I/O & Peripheral Pin ACT (General)
15DTR1/ TNOW1/ GPIO9I/OMultiplexed I/O & Peripheral Pin DTR1/ TNOW1/ GPIO9 (UART)
16TXD6I/OTXD6 (UART)
17RXD6I/ORXD6 (UART)
18TXD3I/OTXD3 (UART)
19RXD3I/ORXD3 (UART)
20GNDGNDGround Reference Pin (GND)
21TXD2I/OTXD2 (UART)
22RXD2I/ORXD2 (UART)
23CTS1/ GPIO2I/OMultiplexed I/O & Peripheral Pin CTS1/ GPIO2 (UART)
24RTS1/ GPIO3I/OMultiplexed I/O & Peripheral Pin RTS1/ GPIO3 (UART)
25CTS3/GPIO6I/OMultiplexed I/O & Peripheral Pin CTS3/GPIO6 (UART)
26CTS2/GPIO4I/OMultiplexed I/O & Peripheral Pin CTS2/GPIO4 (UART)
27RTS2/GPIO5I/OMultiplexed I/O & Peripheral Pin RTS2/GPIO5 (UART)
28RTS3/GPIO7I/OMultiplexed I/O & Peripheral Pin RTS3/GPIO7 (UART)
29ACTI/OMultiplexed I/O & Peripheral Pin ACT (General)
30TXD0I/OTXD0 (UART)
31CTS6/ GPIO16I/OMultiplexed I/O & Peripheral Pin CTS6/ GPIO16 (UART)
32RTS6/ GPIO17I/OMultiplexed I/O & Peripheral Pin RTS6/ GPIO17 (UART)
33RTS0/GPIO1I/OMultiplexed I/O & Peripheral Pin RTS0/GPIO1 (UART)
34DTR0/ TNOW0/ GPIO8I/OMultiplexed I/O & Peripheral Pin DTR0/ TNOW0/ GPIO8 (UART)
35CTS7/ GPIO18I/OMultiplexed I/O & Peripheral Pin CTS7/ GPIO18 (UART)
36RTS7/ GPIO19I/OMultiplexed I/O & Peripheral Pin RTS7/ GPIO19 (UART)
37TXD7I/OTXD7 (UART)
38DSR7/ GPIO45I/OMultiplexed I/O & Peripheral Pin DSR7/ GPIO45 (UART)
39DCD7/ GPIO46I/OMultiplexed I/O & Peripheral Pin DCD7/ GPIO46 (General)
40RI7/ GPIO47I/OMultiplexed I/O & Peripheral Pin RI7/ GPIO47 (General)
41DSR6/ GPIO42I/OMultiplexed I/O & Peripheral Pin DSR6/ GPIO42 (UART)
42DCD6/ GPIO43I/OMultiplexed I/O & Peripheral Pin DCD6/ GPIO43 (General)
43RI6/ GPIO44I/OMultiplexed I/O & Peripheral Pin RI6/ GPIO44 (General)
44DSR3/ GPIO33I/OMultiplexed I/O & Peripheral Pin DSR3/ GPIO33 (UART)
45DCD3/ GPIO34I/OMultiplexed I/O & Peripheral Pin DCD3/ GPIO34 (General)
46RI3/ GPIO35I/OMultiplexed I/O & Peripheral Pin RI3/ GPIO35 (General)
47GNDGNDGround Reference Pin (GND)
48VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
PIN 1 DCD5/ GPIO40
I/O
Multiplexed I/O & Peripheral Pin DCD5/ GPIO40 (General)
Design note: Signal terminal DCD5/ GPIO40 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD5/ GPIO40. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH348Q (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH348Q (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH348Q (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH348Q (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH348Q (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH348Q (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH348Q (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH348
P1 · p01_fig011664×1202px
CH348Q (LQFP-48(7x7)) — l 480Mbps 高速USB 设备接口，外围元器件只需晶体和电容。 l 内置固件，仿真标准串口，用于升级原串口外围设备，或者通过USB 增加额外串口。
l 480Mbps 高速USB 设备接口，外围元器件只需晶体和电容。 l 内置固件，仿真标准串口，用于升级原串口外围设备，或者通过USB 增加额外串口。
P2 · p02_fig011032×1043px
CH348Q (LQFP-48(7x7)) — 3、封装
3、封装
P2 · p02_fig021313×1308px
CH348Q (LQFP-48(7x7)) — CTS1/GPIO2 10
CTS1/GPIO2 10
P8 · p08_fig011726×1721px
CH348Q (LQFP-48(7x7)) — 下图是由CH348 芯片实现的USB 转八路TTL 串口的参考电路图。图中的信号线可以只连接RXDx、 TXDx 以及公共地线，其它信号线CTSx、RTSx、TNOWx 根据需要选用，不需要时都可以悬空。
下图是由CH348 芯片实现的USB 转八路TTL 串口的参考电路图。图中的信号线可以只连接RXDx、 TXDx 以及公共地线，其它信号线CTSx、RTSx、TNOWx 根据需要选用，不需要时都可以悬空。
P8 · p08_fig01P8
CH348Q (LQFP-48(7x7)) — Datasheet Page 8 (p08_fig01)
Datasheet Page 8 (p08_fig01)
P9 · p09_fig011916×1650px
CH348Q (LQFP-48(7x7)) — CH348 手册 ９ | C8 | 0.1uF | C7 0.1uF | R2 | 4K7 | +3V3 | X1 8MHz C5 | 22pF | C6 | 22pF | XI | XO | R1 | 4K7 | +5V 1 | GND 4 | GND 6 | UD+ 3 | UD- 2 | GND 5 | P1 | PC | UD+ UD- VUSB | F1 | 500mA | +3V3 | VIN 3 | GND 1 | VOUT 2 U1 | 1117_3V3 |
CH348 手册 ９ | C8 | 0.1uF | C7 0.1uF | R2 | 4K7 | +3V3 | X1 8MHz C5 | 22pF | C6 | 22pF | XI | XO | R1 | 4K7 | +5V 1 | GND 4 | GND 6 | UD+ 3 | UD- 2 | GND 5 | P1 | PC | UD+ UD- VUSB | F1 | 500mA | +3V3 | VIN 3 | GND 1 | VOUT 2 U1 | 1117_3V3 |

Technical Specifications & Part Details (CH348Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH348Q (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH348Q (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH348Q (LQFP-48(7x7))?

Manufactured by WCH, the CH348Q is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (DCD5/ GPIO40: Multiplexed I/O & Peripheral Pin DCD5/ GPIO40 (General)), 2 (RI5/ GPIO41: Multiplexed I/O & Peripheral Pin RI5/ GPIO41 (General)), 3 (DSR1/ GPIO27: Multiplexed I/O & Peripheral Pin DSR1/ GPIO27 (UART)), 4 (DCD1/ GPIO28: Multiplexed I/O & Peripheral Pin DCD1/ GPIO28 (General)), 5 (RI1/ GPIO29: Multiplexed I/O & Peripheral Pin RI1/ GPIO29 (General)), 6 (XO: Multiplexed I/O & Peripheral Pin XO (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH348Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH348Q (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH348Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH348Q (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH348 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DCD5/ GPIO40Digital_IOSignal terminal DCD5/ GPIO40 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD5/ GPIO40. Supported peripheral buses: General.
2RI5/ GPIO41Digital_IOSignal terminal RI5/ GPIO41 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI5/ GPIO41. Supported peripheral buses: General.
3DSR1/ GPIO27Digital_IOSignal terminal DSR1/ GPIO27 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR1/ GPIO27. Supported peripheral buses: UART.
4DCD1/ GPIO28Digital_IOSignal terminal DCD1/ GPIO28 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD1/ GPIO28. Supported peripheral buses: General.
5RI1/ GPIO29Digital_IOSignal terminal RI1/ GPIO29 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI1/ GPIO29. Supported peripheral buses: General.
6XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
7CFGDigital_IOSignal terminal CFG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG. Supported peripheral buses: General.
8GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
9NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
10CTS1/GPIO2Digital_IOSignal terminal CTS1/GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1/GPIO2. Supported peripheral buses: UART.
11RTS1/GPIO3Digital_IOSignal terminal RTS1/GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS1/GPIO3. Supported peripheral buses: UART.
12TXD1Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
13RXD1Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
14ACTDigital_IOSignal terminal ACT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACT. Supported peripheral buses: General.
15DTR1/ TNOW1/ GPIO9Digital_IOSignal terminal DTR1/ TNOW1/ GPIO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR1/ TNOW1/ GPIO9. Supported peripheral buses: UART.
16TXD6Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
17RXD6Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
18TXD3Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
19RXD3Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
20GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
21TXD2Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
22RXD2Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
23CTS1/ GPIO2Digital_IOSignal terminal CTS1/ GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1/ GPIO2. Supported peripheral buses: UART.
24RTS1/ GPIO3Digital_IOSignal terminal RTS1/ GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS1/ GPIO3. Supported peripheral buses: UART.
25CTS3/GPIO6Digital_IOSignal terminal CTS3/GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS3/GPIO6. Supported peripheral buses: UART.
26CTS2/GPIO4Digital_IOSignal terminal CTS2/GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS2/GPIO4. Supported peripheral buses: UART.
27RTS2/GPIO5Digital_IOSignal terminal RTS2/GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS2/GPIO5. Supported peripheral buses: UART.
28RTS3/GPIO7Digital_IOSignal terminal RTS3/GPIO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS3/GPIO7. Supported peripheral buses: UART.
29ACTDigital_IOSignal terminal ACT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACT. Supported peripheral buses: General.
30TXD0Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
31CTS6/ GPIO16Digital_IOSignal terminal CTS6/ GPIO16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS6/ GPIO16. Supported peripheral buses: UART.
32RTS6/ GPIO17Digital_IOSignal terminal RTS6/ GPIO17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS6/ GPIO17. Supported peripheral buses: UART.
33RTS0/GPIO1Digital_IOSignal terminal RTS0/GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS0/GPIO1. Supported peripheral buses: UART.
34DTR0/ TNOW0/ GPIO8Digital_IOSignal terminal DTR0/ TNOW0/ GPIO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR0/ TNOW0/ GPIO8. Supported peripheral buses: UART.
35CTS7/ GPIO18Digital_IOSignal terminal CTS7/ GPIO18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS7/ GPIO18. Supported peripheral buses: UART.
36RTS7/ GPIO19Digital_IOSignal terminal RTS7/ GPIO19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS7/ GPIO19. Supported peripheral buses: UART.
37TXD7Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
38DSR7/ GPIO45Digital_IOSignal terminal DSR7/ GPIO45 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR7/ GPIO45. Supported peripheral buses: UART.
39DCD7/ GPIO46Digital_IOSignal terminal DCD7/ GPIO46 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD7/ GPIO46. Supported peripheral buses: General.
40RI7/ GPIO47Digital_IOSignal terminal RI7/ GPIO47 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI7/ GPIO47. Supported peripheral buses: General.
41DSR6/ GPIO42Digital_IOSignal terminal DSR6/ GPIO42 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR6/ GPIO42. Supported peripheral buses: UART.
42DCD6/ GPIO43Digital_IOSignal terminal DCD6/ GPIO43 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD6/ GPIO43. Supported peripheral buses: General.
43RI6/ GPIO44Digital_IOSignal terminal RI6/ GPIO44 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI6/ GPIO44. Supported peripheral buses: General.
44DSR3/ GPIO33Digital_IOSignal terminal DSR3/ GPIO33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR3/ GPIO33. Supported peripheral buses: UART.
45DCD3/ GPIO34Digital_IOSignal terminal DCD3/ GPIO34 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD3/ GPIO34. Supported peripheral buses: General.
46RI3/ GPIO35Digital_IOSignal terminal RI3/ GPIO35 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI3/ GPIO35. Supported peripheral buses: General.
47GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
48VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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