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CH32X035C8T6 (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32X035C8T6

WCHID: C29779902LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32X035C8T6 (LQFP-48(7x7))1PA15/TX2_2PA16 I/O PA13PA17 I/O PA14PA18 I/O PA15PA19 I/O PA16PA20 I/O PA27PA21 I/O PA28PC0 I/O/A PC9PC1 I/O/A PC10PC2 I/O/A PC11IO612IO713PA23 I/O/A P14PA0 I/O/A PA15IO1716IO1817PA3 I/O/A PA18PC4 I/O PC419PC5 I/O PC520PA4 I/O/A PA21PA5 I/O/A PA22PA6 I/O/A PA23IO1224IO1348VDD47GND46IO4645IO4544IO4443IO4342IO4241IO4140PA8/RTS4/RTS39PC15/CC2/T2C38PC14/CC1/T1C37IO3736PB13/TX4_35PB12/T1C4_/T34IO3433IO3332IO3231PB11/T1C3/T230PB10/TX1/T1C29PB9/T1C1/MCO28PB8/T1C3N/O127PB7/T1C2N/RT26PB6/T1C1N/CT25PB5/O1O1/T3CGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.835.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA15/TX2_I/OMultiplexed I/O & Peripheral Pin PA15/TX2_ (General)
2PA16 I/O PA16I/OMultiplexed I/O & Peripheral Pin PA16 I/O PA16 (General)
3PA17 I/O PA17I/OMultiplexed I/O & Peripheral Pin PA17 I/O PA17 (UART)
4PA18 I/O PA18I/OMultiplexed I/O & Peripheral Pin PA18 I/O PA18 (General)
5PA19 I/O PA19I/OMultiplexed I/O & Peripheral Pin PA19 I/O PA19 (General)
6PA20 I/O PA20I/OMultiplexed I/O & Peripheral Pin PA20 I/O PA20 (General)
7PA21 I/O PA21I/OMultiplexed I/O & Peripheral Pin PA21 I/O PA21 (UART)
8PC0 I/O/A PC0I/OMultiplexed I/O & Peripheral Pin PC0 I/O/A PC0 (General)
9PC1 I/O/A PC1I/OMultiplexed I/O & Peripheral Pin PC1 I/O/A PC1 (General)
10PC2 I/O/A PC2I/OMultiplexed I/O & Peripheral Pin PC2 I/O/A PC2 (UART)
11IO6I/OGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12IO7I/OGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13PA23 I/O/A PA23I/OMultiplexed I/O & Peripheral Pin PA23 I/O/A PA23 (General)
14PA0 I/O/A PA0I/OMultiplexed I/O & Peripheral Pin PA0 I/O/A PA0 (UART)
15IO17I/OGPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16IO18I/OGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17PA3 I/O/A PA3I/OMultiplexed I/O & Peripheral Pin PA3 I/O/A PA3 (UART)
18PC4 I/O PC4I/OMultiplexed I/O & Peripheral Pin PC4 I/O PC4 (General)
19PC5 I/O PC5I/OMultiplexed I/O & Peripheral Pin PC5 I/O PC5 (SPI)
20PA4 I/O/A PA4I/OMultiplexed I/O & Peripheral Pin PA4 I/O/A PA4 (UART)
21PA5 I/O/A PA5I/OMultiplexed I/O & Peripheral Pin PA5 I/O/A PA5 (UART, SPI)
22PA6 I/O/A PA6I/OMultiplexed I/O & Peripheral Pin PA6 I/O/A PA6 (UART, SPI)
23IO12I/OGPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24IO13I/OGPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25PB5/O1O1/T3C2_/T1BKI/OMultiplexed I/O & Peripheral Pin PB5/O1O1/T3C2_/T1BK (General)
26PB6/T1C1N/CTS3/O1N1I/OMultiplexed I/O & Peripheral Pin PB6/T1C1N/CTS3/O1N1 (UART)
27PB7/T1C2N/RTS3_/O2P2I/OMultiplexed I/O & Peripheral Pin PB7/T1C2N/RTS3_/O2P2 (UART)
28PB8/T1C3N/O1P1I/OMultiplexed I/O & Peripheral Pin PB8/T1C3N/O1P1 (General)
29PB9/T1C1/MCO/TX4_I/OMultiplexed I/O & Peripheral Pin PB9/T1C1/MCO/TX4_ (RTC/CLK)
30PB10/TX1/T1C2I/OMultiplexed I/O & Peripheral Pin PB10/TX1/T1C2 (General)
31PB11/T1C3/T2C1N_/RX1I/OMultiplexed I/O & Peripheral Pin PB11/T1C3/T2C1N_/RX1 (General)
32IO32I/OGeneral Purpose Digital I/O Pin IO32
33IO33I/OGeneral Purpose Digital I/O Pin IO33
34IO34I/OGeneral Purpose Digital I/O Pin IO34
35PB12/T1C4_/T2C2N_I/OMultiplexed I/O & Peripheral Pin PB12/T1C4_/T2C2N_ (General)
36PB13/TX4_I/OMultiplexed I/O & Peripheral Pin PB13/TX4_ (General)
37IO37I/OGeneral Purpose Digital I/O Pin IO37
38PC14/CC1/T1C3_/T2C2_I/OMultiplexed I/O & Peripheral Pin PC14/CC1/T1C3_/T2C2_ (General)
39PC15/CC2/T2C3_/T1ET_I/OMultiplexed I/O & Peripheral Pin PC15/CC2/T2C3_/T1ET_ (General)
40PA8/RTS4/RTS1_I/OMultiplexed I/O & Peripheral Pin PA8/RTS4/RTS1_ (UART)
41IO41I/OGeneral Purpose Digital I/O Pin IO41
42IO42I/OGeneral Purpose Digital I/O Pin IO42
43IO43I/OGeneral Purpose Digital I/O Pin IO43
44IO44I/OGeneral Purpose Digital I/O Pin IO44
45IO45I/OGeneral Purpose Digital I/O Pin IO45
46IO46I/OGeneral Purpose Digital I/O Pin IO46
47GNDGNDGround Reference Pin (GND)
48VDDPowerPower Supply Input (VDD — 2V~5.5V)
PIN 1 PA15/TX2_
I/O
Multiplexed I/O & Peripheral Pin PA15/TX2_ (General)
Design note: Signal terminal PA15/TX2_ (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA15/TX2_. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32X035C8T6 (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32X035C8T6 (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32X035C8T6 (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32X035C8T6 (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32X035C8T6 (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32X035C8T6 (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32X035C8T6 (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH32X035 / CH32X033
P17 · p17_fig01EXACT PACKAGE
CH32X035C8T6 (LQFP-48(7x7)) — V2.2 15
V2.2 15
P18 · p18_fig01EXACT PACKAGE
CH32X035C8T6 (LQFP-48(7x7)) — V2.2 16
V2.2 16
P2 · p02_fig011815×850px
CH32X035C8T6 (LQFP-48(7x7)) — 型号 Code Flash RAM | 通 用 I/O | 高 级 定 时 器 | 通 用 定 时 | 器 | 串 口 | 看 门 狗 | PDUSB | ADC | OPA | 运 放 | CMP 比较 | 器 | 电容 触摸 按键 | SPI | PIOC 单线 接口 | 封装 形式 USB | 主 机 | USB | 设 备 | Type-C Source | Sink | DRP | CH32X035R8T6 62K 20K 60 2 1 4 2 √ √ √ 14+1
型号 Code Flash RAM | 通 用 I/O | 高 级 定 时 器 | 通 用 定 时 | 器 | 串 口 | 看 门 狗 | PDUSB | ADC | OPA | 运 放 | CMP 比较 | 器 | 电容 触摸 按键 | SPI | PIOC 单线 接口 | 封装 形式 USB | 主 机 | USB | 设 备 | Type-C Source | Sink | DRP | CH32X035R8T6 62K 20K 60 2 1 4 2 √ √ √ 14+1
P11 · p11_fig011874×1871px
CH32X035C8T6 (LQFP-48(7x7)) — 第2 章 引脚信息
第2 章 引脚信息
P11 · p11_fig01P11
CH32X035C8T6 (LQFP-48(7x7)) — Datasheet Page 11 (p11_fig01)
Datasheet Page 11 (p11_fig01)
P18 · p18_fig01P18
CH32X035C8T6 (LQFP-48(7x7)) — Datasheet Page 18 (p18_fig01)
Datasheet Page 18 (p18_fig01)

Technical Specifications & Part Details (CH32X035C8T6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH32X035C8T6 (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2V~5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2V~5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32X035C8T6 (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32X035C8T6 (LQFP-48(7x7))?

Manufactured by WCH, the CH32X035C8T6 is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2V~5.5V. Key pins include: 1 (PA15/TX2_: Multiplexed I/O & Peripheral Pin PA15/TX2_ (General)), 2 (PA16 I/O PA16: Multiplexed I/O & Peripheral Pin PA16 I/O PA16 (General)), 3 (PA17 I/O PA17: Multiplexed I/O & Peripheral Pin PA17 I/O PA17 (UART)), 4 (PA18 I/O PA18: Multiplexed I/O & Peripheral Pin PA18 I/O PA18 (General)), 5 (PA19 I/O PA19: Multiplexed I/O & Peripheral Pin PA19 I/O PA19 (General)), 6 (PA20 I/O PA20: Multiplexed I/O & Peripheral Pin PA20 I/O PA20 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH32X035C8T6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32X035C8T6 (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32X035C8T6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32X035C8T6 (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH32X035 / CH32X033 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA15/TX2_Digital_IOSignal terminal PA15/TX2_ (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA15/TX2_. Supported peripheral buses: General.
2PA16 I/O PA16Digital_IOSignal terminal PA16 I/O PA16 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA16 I/O PA16. Supported peripheral buses: General.
3PA17 I/O PA17Digital_IOSignal terminal PA17 I/O PA17 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA17 I/O PA17. Supported peripheral buses: UART.
4PA18 I/O PA18Digital_IOSignal terminal PA18 I/O PA18 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA18 I/O PA18. Supported peripheral buses: General.
5PA19 I/O PA19Digital_IOSignal terminal PA19 I/O PA19 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA19 I/O PA19. Supported peripheral buses: General.
6PA20 I/O PA20Digital_IOSignal terminal PA20 I/O PA20 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA20 I/O PA20. Supported peripheral buses: General.
7PA21 I/O PA21Digital_IOSignal terminal PA21 I/O PA21 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA21 I/O PA21. Supported peripheral buses: UART.
8PC0 I/O/A PC0Digital_IOSignal terminal PC0 I/O/A PC0 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PC0 I/O/A PC0. Supported peripheral buses: General.
9PC1 I/O/A PC1Digital_IOSignal terminal PC1 I/O/A PC1 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PC1 I/O/A PC1. Supported peripheral buses: General.
10PC2 I/O/A PC2Digital_IOSignal terminal PC2 I/O/A PC2 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PC2 I/O/A PC2. Supported peripheral buses: UART.
11IO6Digital_IOGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12IO7Digital_IOGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13PA23 I/O/A PA23Digital_IOSignal terminal PA23 I/O/A PA23 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA23 I/O/A PA23. Supported peripheral buses: General.
14PA0 I/O/A PA0Digital_IOSignal terminal PA0 I/O/A PA0 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA0 I/O/A PA0. Supported peripheral buses: UART.
15IO17Digital_IOGPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16IO18Digital_IOGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17PA3 I/O/A PA3Digital_IOSignal terminal PA3 I/O/A PA3 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA3 I/O/A PA3. Supported peripheral buses: UART.
18PC4 I/O PC4Digital_IOSignal terminal PC4 I/O PC4 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PC4 I/O PC4. Supported peripheral buses: General.
19PC5 I/O PC5Digital_IOSignal terminal PC5 I/O PC5 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PC5 I/O PC5. Supported peripheral buses: SPI.
20PA4 I/O/A PA4Digital_IOSignal terminal PA4 I/O/A PA4 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA4 I/O/A PA4. Supported peripheral buses: UART.
21PA5 I/O/A PA5Digital_IOSignal terminal PA5 I/O/A PA5 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA5 I/O/A PA5. Supported peripheral buses: UART, SPI.
22PA6 I/O/A PA6Digital_IOSignal terminal PA6 I/O/A PA6 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA6 I/O/A PA6. Supported peripheral buses: UART, SPI.
23IO12Digital_IOGPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24IO13Digital_IOGPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25PB5/O1O1/T3C2_/T1BKDigital_IOSignal terminal PB5/O1O1/T3C2_/T1BK (I/O, 2V~5.5V domain). Multiplexed alternate functions: PB5/O1O1/T3C2_/T1BK. Supported peripheral buses: General.
26PB6/T1C1N/CTS3/O1N1Digital_IOSignal terminal PB6/T1C1N/CTS3/O1N1 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PB6/T1C1N/CTS3/O1N1. Supported peripheral buses: UART.
27PB7/T1C2N/RTS3_/O2P2Digital_IOSignal terminal PB7/T1C2N/RTS3_/O2P2 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PB7/T1C2N/RTS3_/O2P2. Supported peripheral buses: UART.
28PB8/T1C3N/O1P1Digital_IOSignal terminal PB8/T1C3N/O1P1 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PB8/T1C3N/O1P1. Supported peripheral buses: General.
29PB9/T1C1/MCO/TX4_Digital_IOSignal terminal PB9/T1C1/MCO/TX4_ (I/O, 2V~5.5V domain). Multiplexed alternate functions: PB9/T1C1/MCO/TX4_. Supported peripheral buses: RTC/CLK.
30PB10/TX1/T1C2Digital_IOSignal terminal PB10/TX1/T1C2 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PB10/TX1/T1C2. Supported peripheral buses: General.
31PB11/T1C3/T2C1N_/RX1Digital_IOSignal terminal PB11/T1C3/T2C1N_/RX1 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PB11/T1C3/T2C1N_/RX1. Supported peripheral buses: General.
32IO32Digital_IOGeneral Purpose Digital I/O Pin IO32
33IO33Digital_IOGeneral Purpose Digital I/O Pin IO33
34IO34Digital_IOGeneral Purpose Digital I/O Pin IO34
35PB12/T1C4_/T2C2N_Digital_IOSignal terminal PB12/T1C4_/T2C2N_ (I/O, 2V~5.5V domain). Multiplexed alternate functions: PB12/T1C4_/T2C2N_. Supported peripheral buses: General.
36PB13/TX4_Digital_IOSignal terminal PB13/TX4_ (I/O, 2V~5.5V domain). Multiplexed alternate functions: PB13/TX4_. Supported peripheral buses: General.
37IO37Digital_IOGeneral Purpose Digital I/O Pin IO37
38PC14/CC1/T1C3_/T2C2_Digital_IOSignal terminal PC14/CC1/T1C3_/T2C2_ (I/O, 2V~5.5V domain). Multiplexed alternate functions: PC14/CC1/T1C3_/T2C2_. Supported peripheral buses: General.
39PC15/CC2/T2C3_/T1ET_Digital_IOSignal terminal PC15/CC2/T2C3_/T1ET_ (I/O, 2V~5.5V domain). Multiplexed alternate functions: PC15/CC2/T2C3_/T1ET_. Supported peripheral buses: General.
40PA8/RTS4/RTS1_Digital_IOSignal terminal PA8/RTS4/RTS1_ (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA8/RTS4/RTS1_. Supported peripheral buses: UART.
41IO41Digital_IOGeneral Purpose Digital I/O Pin IO41
42IO42Digital_IOGeneral Purpose Digital I/O Pin IO42
43IO43Digital_IOGeneral Purpose Digital I/O Pin IO43
44IO44Digital_IOGeneral Purpose Digital I/O Pin IO44
45IO45Digital_IOGeneral Purpose Digital I/O Pin IO45
46IO46Digital_IOGeneral Purpose Digital I/O Pin IO46
47GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
48VDDPower_InPrimary positive power supply input (VDD) operating in the 2V~5.5V domain (Max rating: 5.5V).
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