Mechanical Dimensions & Land Pattern (SOP-8)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| C1 BOM | 100nF (0.1µF) 50V X7R 0402 / 0603 | Internal 3.3V LDO cap at V3 (Pin 4) — to GND at VCC=5V, or tie V3 directly to VCC at 3.3V. |
| C2, C3 BOM | 100nF + 10µF 0603 | Main VCC supply decoupling (Pin 16) from USB VBUS — place < 2mm from Pin 16. |
| Y1 + C4, C5 BOM | 12MHz Crystal + 2× 22pF NP0 HC-49S / SMD-3225 + 0603 | Mandatory 12MHz crystal for CH340G (Pins 7/8) — switch to CH340C to eliminate this crystal. |
| CH340C WCH | 100% Drop-in | 100% Pin-to-Pin SOP-16 (Built-in 12MHz clock) — shares SOP-16 PCB footprint with CH340G; leave Y1/22pF DNI. |
| CH340G WCH | 100% Drop-in | 100% Pin-to-Pin SOP-16 — requires external 12MHz crystal + two 22pF load caps on Pins 7-8. |
| CH340B WCH | 100% Drop-in | 100% Pin-to-Pin SOP-16 (Built-in 12MHz clock) — shares SOP-16 PCB footprint with CH340G; leave Y1/22pF DNI. |
Technical Frequently Asked Questions (FAQ) — CH340N (SOP-8)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH340N (SOP-8)?
Manufactured by WCH, the CH340N is housed in a SOP-8 package with 8 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)), 2 (UD-: Multiplexed I/O & Peripheral Pin UD- (USB)), 3 (GND: Ground Reference Pin (GND)), 4 (RTS#: Multiplexed I/O & Peripheral Pin RTS# (UART)), 5 (VCC: Power Supply Input (VCC — 3.3V / 5.0V USB-UART Domain)), 6 (TXD: TXD (UART)).
What are the IPC-7351B PCB Footprint dimensions for CH340N?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH340N (SOP-8) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 8 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH340N?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH340N (WCH, SOP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (8 pins) & CH340 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | UD+ | Digital_IO | Signal terminal UD+ (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB. |
| 2 | UD- | Digital_IO | Signal terminal UD- (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB. |
| 3 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | RTS# | Digital_IO | Signal terminal RTS# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: RTS#. Supported peripheral buses: UART. |
| 5 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 3.3V / 5.0V USB-UART Domain domain (Max rating: 5.5V). |
| 6 | TXD | Digital_IO | Asynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin. |
| 7 | RXD | Digital_IO | Asynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors. |
| 8 | V3 | Power_Out | Internal 3.3V LDO regulator node: connect to VCC when powered at 3.3V; connect a 100nF decoupling capacitor to GND when powered at 5V. |