STM32F042G6U6TR (UFQFN-28) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of STM32F042G6U6TR (UFQFN-28)?

Manufactured by ST, the STM32F042G6U6TR is housed in a UFQFN-28 package with 29 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2 V to 3.6 V. Key pins include: 1 (PB8BOOT0 -: Multiplexed I/O & Peripheral Pin PB8BOOT0 - (I2C, CAN)), 2 (PF0OSC IN -_ (PF0): Multiplexed I/O & Peripheral Pin PF0OSC IN -_ (PF0) (I2C, RTC/CLK)), 3 (PF1OSC OUT -_ (PF1): Multiplexed I/O & Peripheral Pin PF1OSC OUT -_ (PF1) (I2C, RTC/CLK)), 4 (NRST: System Enable & Hardware Reset (NRST)), 5 (10 -Jan-2017: Multiplexed I/O & Peripheral Pin 10 -Jan-2017 (General)), 6 (PA0: Multiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)).

Q: What are the IPC-7351B PCB Footprint dimensions for STM32F042G6U6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F042G6U6TR (UFQFN-28) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 3.30 × 3.30 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F042G6U6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F042G6U6TR (ST, UFQFN-28) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	PB8BOOT0 -	I/O	Multiplexed I/O & Peripheral Pin PB8BOOT0 - (I2C, CAN)
2	PF0OSC IN -_ (PF0)	I/O	Multiplexed I/O & Peripheral Pin PF0OSC IN -_ (PF0) (I2C, RTC/CLK)
3	PF1OSC OUT -_ (PF1)	I/O	Multiplexed I/O & Peripheral Pin PF1OSC OUT -_ (PF1) (I2C, RTC/CLK)
4	NRST	I	System Enable & Hardware Reset (NRST)
5	10 -Jan-2017	I/O	Multiplexed I/O & Peripheral Pin 10 -Jan-2017 (General)
6	PA0	I/O	Multiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
7	PA1	I/O	Multiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
8	PA2	I/O	Multiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
9	PA3	I/O	Multiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
10	PA4	I/O	Multiplexed I/O & Peripheral Pin PA4 (USB, UART, SPI, ADC)
11	PA5	I/O	Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
12	PA6	I/O	Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
13	PA7	I/O	Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
14	PB0	I/O	Multiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
15	PB1	I/O	Multiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
16	VSS	GND	Ground Reference Pin (VSS)
17	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
18	VDDIO2	Power	Power Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
19	PA9	I/O	Multiplexed I/O & Peripheral Pin PA9 (UART, I2C, PWM)
20	PA10	I/O	Multiplexed I/O & Peripheral Pin PA10 (UART, I2C, PWM)
21	PA13	I/O	Multiplexed I/O & Peripheral Pin PA13 (USB)
22	PA14	I/O	Multiplexed I/O & Peripheral Pin PA14 (UART)
23	PA15	I/O	Multiplexed I/O & Peripheral Pin PA15 (USB, UART, SPI, PWM)
24	PB3	I/O	Multiplexed I/O & Peripheral Pin PB3 (SPI, PWM)
25	PB4	I/O	Multiplexed I/O & Peripheral Pin PB4 (SPI, PWM)
26	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C, PWM)
27	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (UART, I2C)
28	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (UART, I2C)
29	EPAD/GND	GND	Ground Reference Pin (EPAD/GND)

PIN 1 PB8BOOT0 -

I/O

Multiplexed I/O & Peripheral Pin PB8BOOT0 - (I2C, CAN)

Design note: Alt: I2C1_SCLCEC , , TIM16_CH1 , TSC_SYNC , CAN_RX | Add: Bootmemory selection

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 32 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

STM32F042G6U6TR (UFQFN-28) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

STM32F042G6U6TR (UFQFN-28) - 2. Standard Pinout (Top View)

True package pinout (29 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

STM32F042G6U6TR (UFQFN-28) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

STM32F042G6U6TR (UFQFN-28) - 4. Package Dimensions (D×E×A)

UFQFN-28 · 5.00×5.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

STM32F042G6U6TR (UFQFN-28) - 5. Recommended Land Pattern

IPC-7351B Footprint (29 Pads)Expand ›

6. Application SchematicSCHEMATIC

STM32F042G6U6TR (UFQFN-28) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (32 figures · Page 1/3)

Showing 1–12 of 32 uncropped original figures for STM32F042

P1 · p01_fig01EXACT PACKAGE

STM32F042G6U6TR (UFQFN-28) — ARM®-based 32-bit MCU, up to 32 KB Flash, crystal-less USB FS 2.0, CAN, 9 timers, ADC and comm. interfaces, 2.0 - 3.6 V | Datasheet - production data | LQFP48 7x7 mm UFQFPN48 7x7 mm WLCSP36 UFQFPN32 5x5 mm UFQFPN28 4x4 mm | TSSOP20 LQFP32 7

ARM®-based 32-bit MCU, up to 32 KB Flash, crystal-less USB FS 2.0, CAN, 9 timers, ADC and comm. interfaces, 2.0 - 3.6 V | Datasheet - production data | LQFP48 7x7 mm UFQFPN48 7x7 mm WLCSP36 UFQFPN32 5x5 mm UFQFPN28 4x4 mm | TSSOP20 LQFP32 7

P105 · p105_fig01EXACT PACKAGE

Figure 48. UFQFPN28 package outline

P106 · p106_fig01EXACT PACKAGE

Figure 49. Recommended footprint for UFQFPN28 package

P43 · p43_fig011546×1755px

Figure 13. Power supply scheme

P43 · p43_fig01P43

Datasheet Page 43 (p43_fig01)

P63 · p63_fig011546×718px

Figure 17. Typical application with an 8 MHz crystal

P81 · p81_fig011751×902px

Figure 26. ADC accuracy characteristics

P81 · p81_fig021546×667px

Figure 27. Typical connection diagram using the ADC

P97 · p97_fig011546×1088px

Figure 40. Recommended pad footprint for WLCSP36 package

P105 · p105_fig01P105

Datasheet Page 105 (p105_fig01)

P106 · p106_fig01P106

Datasheet Page 106 (p106_fig01)

P114 · p114_fig011548×2185px

114/117 DocID025832 Rev 5

Page 1 / 3 (32 extracted figures)

Technical Specifications & Part Details (STM32F042G6U6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Embedded Microcontroller Unit (MCU)

Detailed Overview:STM32F042G6U6TR (UFQFN-28) is a 28-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

2 V to 3.6 V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

48 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

13 5V-tolerant (FT) pins detected

Package Envelope (D × E × A)D × E × A

5.00 × 5.00 × 0.85 mm (A1=0.03 mm)

Package family: QFN (UFQFN-28)

Pin Count & Lead PitchN / e

28 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Boot Strapping Pin Alert (PB8BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol29 auto-grouped pins

IPC-7351B Land Pattern29 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteEPAD 3.30×3.30mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

IPC-7351B

49P7.0×7.0×0.55mmP=0.5mm

STM32F042 (UFQFPN-48(7x7))

Mechanical Dimensions & Land Pattern (UFQFN-28)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

5.00 × 5.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.85mm · e=0.50mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit UFQFN-28	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F042G6U6TR (UFQFN-28)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F042G6U6TR (UFQFN-28)?

Manufactured by ST, the STM32F042G6U6TR is housed in a UFQFN-28 package with 29 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2 V to 3.6 V. Key pins include: 1 (PB8BOOT0 -: Multiplexed I/O & Peripheral Pin PB8BOOT0 - (I2C, CAN)), 2 (PF0OSC IN -_ (PF0): Multiplexed I/O & Peripheral Pin PF0OSC IN -_ (PF0) (I2C, RTC/CLK)), 3 (PF1OSC OUT -_ (PF1): Multiplexed I/O & Peripheral Pin PF1OSC OUT -_ (PF1) (I2C, RTC/CLK)), 4 (NRST: System Enable & Hardware Reset (NRST)), 5 (10 -Jan-2017: Multiplexed I/O & Peripheral Pin 10 -Jan-2017 (General)), 6 (PA0: Multiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32F042G6U6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F042G6U6TR (UFQFN-28) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 3.30 × 3.30 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F042G6U6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F042G6U6TR (ST, UFQFN-28) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & STM32F042 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	PB8BOOT0 -	Digital_IO	Signal terminal PB8BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCLCEC. Supported peripheral buses: I2C, CAN.
2	PF0OSC IN -_ (PF0)	Digital_IO	Signal terminal PF0OSC IN -_ (PF0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C, RTC/CLK.
3	PF1OSC OUT -_ (PF1)	Digital_IO	Signal terminal PF1OSC OUT -_ (PF1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C, RTC/CLK.
4	NRST	Digital_IO	Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
5	10 -Jan-2017	Digital_IO	Signal terminal 10 -Jan-2017 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 10 -Jan-2017. Supported peripheral buses: General.
6	PA0	Digital_IO	Signal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
7	PA1	Digital_IO	Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
8	PA2	Digital_IO	Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
9	PA3	Digital_IO	Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
10	PA4	Digital_IO	Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSI2S1WS. Supported peripheral buses: USB, UART, SPI, ADC.
11	PA5	Digital_IO	Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCKI2S1CK. Supported peripheral buses: SPI, ADC, PWM.
12	PA6	Digital_IO	Signal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISOI2S1MCK. Supported peripheral buses: SPI, ADC, PWM.
13	PA7	Digital_IO	Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSII2S1SD. Supported peripheral buses: SPI, ADC, PWM.
14	PB0	Digital_IO	Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
15	PB1	Digital_IO	Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
16	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
18	VDDIO2	Power_In	Primary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
19	PA9	Digital_IO	Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, PWM.
20	PA10	Digital_IO	Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C, PWM.
21	PA13	Digital_IO	Signal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: USB.
22	PA14	Digital_IO	Signal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: UART.
23	PA15	Digital_IO	Signal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSSI2S1WS. Supported peripheral buses: USB, UART, SPI, PWM.
24	PB3	Digital_IO	Signal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCKI2S1CK. Supported peripheral buses: SPI, PWM.
25	PB4	Digital_IO	Signal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOI2S1MCK. Supported peripheral buses: SPI, PWM.
26	PB5	Digital_IO	Signal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSII2S1SD, I2C1_SMBA. Supported peripheral buses: SPI, I2C, PWM.
27	PB6	Digital_IO	Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
28	PB7	Digital_IO	Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
29	EPAD/GND	GND	0V electrical ground return terminal (EPAD/GND) for internal core logic, I/O drivers, and analog sub-blocks.

4D Studio: STM32F042G6U6TR Permalink: /part/C2971720 ST UFQFN-28 All Packages All Manufacturers