Mechanical Dimensions & Land Pattern (LQFP-208(28x28))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
28.00 × 28.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
208P / 208Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-208(28x28) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32F429BET6 (LQFP-208(28x28))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32F429BET6 (LQFP-208(28x28))?
Manufactured by ST, the STM32F429BET6 is housed in a LQFP-208(28x28) package with 208 pins and a 0.50 mm lead pitch. Key pins include: 1 (P1: Multiplexed I/O & Peripheral Pin P1 (General)), 2 (P2: Multiplexed I/O & Peripheral Pin P2 (General)), 3 (P3: Multiplexed I/O & Peripheral Pin P3 (General)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (SPI)), 5 (PE6: Multiplexed I/O & Peripheral Pin PE6 (SPI)), 6 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))).
What are the IPC-7351B PCB Footprint dimensions for STM32F429BET6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F429BET6 (LQFP-208(28x28)) has a nominal body envelope of 28.00 × 28.00 mm, pitch e = 0.50 mm, and 208 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F429BET6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F429BET6 (ST, LQFP-208(28x28)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (208 pins) & STM32F429 / STM32F427 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | P1 | Digital_IO | Signal terminal P1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P1. Supported peripheral buses: General. |
| 2 | P2 | Digital_IO | Signal terminal P2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P2. Supported peripheral buses: General. |
| 3 | P3 | Digital_IO | Signal terminal P3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P3. Supported peripheral buses: General. |
| 4 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI4_MISO. Supported peripheral buses: SPI. |
| 5 | PE6 | Digital_IO | Signal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI4_MOSI. Supported peripheral buses: SPI. |
| 6 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 7 | PI8 | Digital_IO | Signal terminal PI8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PI8. Supported peripheral buses: General. |
| 8 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General. |
| 9 | PC14 - OSC32_IN (PC14) | Digital_IO | Signal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK. |
| 10 | IO5 | Digital_IO | GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4 |
| 11 | PI9 | Digital_IO | Signal terminal PI9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PI9. Supported peripheral buses: CAN. |
| 12 | PI10 | Digital_IO | Signal terminal PI10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PI10. Supported peripheral buses: General. |
| 13 | PI11 | Digital_IO | Signal terminal PI11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PI11. Supported peripheral buses: General. |
| 14 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 15 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 16 | PF0 | Digital_IO | Signal terminal PF0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: I2C. |
| 17 | PF1 | Digital_IO | Signal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: I2C. |
| 18 | PF2 | Digital_IO | Signal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: I2C. |
| 19 | PI12 | Digital_IO | Signal terminal PI12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PI12. Supported peripheral buses: General. |
| 20 | PI13 | Digital_IO | Signal terminal PI13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PI13. Supported peripheral buses: General. |
| 21 | PI14 | Digital_IO | Signal terminal PI14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PI14. Supported peripheral buses: General. |
| 22 | PF3 | Digital_IO | Signal terminal PF3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General. |
| 23 | PF4 | Digital_IO | Signal terminal PF4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General. |
| 24 | PF5 | Digital_IO | Signal terminal PF5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General. |
| 25 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 26 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 27 | PF6 | Digital_IO | Signal terminal PF6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI5_NSS. Supported peripheral buses: UART, SPI. |
| 28 | PF7 | Digital_IO | Signal terminal PF7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI5_SCK. Supported peripheral buses: UART, SPI. |
| 29 | PF8 | Digital_IO | Signal terminal PF8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI5_MISO. Supported peripheral buses: SPI. |
| 30 | PF9 | Digital_IO | Signal terminal PF9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI5_MOSI. Supported peripheral buses: SPI. |
| 31 | PF10 | Digital_IO | Signal terminal PF10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF10. Supported peripheral buses: General. |
| 32 | PH0OSC IN -_ (PH0) | Digital_IO | Signal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: General. |
| 33 | PH1 - OSC_OUT (PH1) | Digital_IO | Signal terminal PH1 - OSC_OUT (PH1) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1 - OSC_OUT (PH1). Supported peripheral buses: RTC/CLK. |
| 34 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 35 | PC0 | Digital_IO | Signal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General. |
| 36 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General. |
| 37 | PC2 | Digital_IO | Signal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI. |
| 38 | PC3 | Digital_IO | Signal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI. |
| 39 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 40 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 41 | VREF+ | Analog | Signal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General. |
| 42 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 43 | PA0WKUP - (PA0) | Digital_IO | Signal terminal PA0WKUP - (PA0) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0WKUP - (PA0). Supported peripheral buses: UART, PWM. |
| 44 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, PWM. |
| 45 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, PWM. |
| 46 | PH2 | Digital_IO | Signal terminal PH2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH2. Supported peripheral buses: General. |
| 47 | PH3 | Digital_IO | Signal terminal PH3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH3. Supported peripheral buses: General. |
| 48 | PH4 | Digital_IO | Signal terminal PH4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: I2C. |
| 49 | PH5 | Digital_IO | Signal terminal PH5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH5. Supported peripheral buses: I2C. |
| 50 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, PWM. |
| 51 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 52 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 53 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI. |
| 54 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, PWM. |
| 55 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, PWM. |
| 56 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, PWM. |
| 57 | PC4 | Digital_IO | Signal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART. |
| 58 | PC5 | Digital_IO | Signal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: UART. |
| 59 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 60 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 61 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: PWM. |
| 62 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: PWM. |
| 63 | PB2BOOT1 - (PB2) | Digital_IO | Signal terminal PB2BOOT1 - (PB2) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2BOOT1 - (PB2). Supported peripheral buses: General. |
| 64 | PI15 | Digital_IO | Signal terminal PI15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PI15. Supported peripheral buses: General. |