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STM32L496VGY6PTR (UFBGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L496VGY6PTR

STID: C2970006UFBGA-100 · 100 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L496VGY6PTR (UFBGA-100)A1PI10A2PH2A3PB8A4PH3BOOT0 -A5PD7A6PD5A7PB4(NJTRST)A8PB3 (JTDO/TRA9PA15(JTDI)A10PA14(JTCK/ SB1PI9B2PI7B3PB9B4PB7B5PB6B6PD6B7PD4B8PD3B9VSSB10PE3C1VDDC2VSSC3PE0C4VDDC5PB5C6PG14C7PG13C8PD2C9PC13C10VBATD1PA11D2PA10D3VSSD4PF2D5PF1D6PF0D7PG12D8PG10D9PG9D10PC14-OSC32_IE1PC8E2PC9E3PA8E4PF3E5PG11E6PB4E7PE4E8PE5E9PC11E10VSSK10VSSK9PA6K8PC5K7PB1K6PE7K5PE8K4PE11K3PB10K2VSSK1PG15J10VDDAJ9PA3J8VDDJ7PA7J6PB0J5PE9J4PE14J3PB11J2PB13J1PB12H10PC2H9VSSAH8PA1H7PA2H6PC4H5PE10H4PE15H3PD8H2PB14H1PB15G10PC0G9PA0G8VREF -G7VDDIO2G6PA5G5PE12G4PE13G3PG11G2PD9G1PD10F10PH0-OSC_INF9PH1-OSC_OUTF8PC12F7VSSF6PA4F5PB2F4PD15F3PC7F2PC6F1VDDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1A2B2C2D2E2F2G2H2J2K2A3B3C3D3E3F3G3H3J3K3A4B4C4D4E4F4G4H4J4K4A5B5C5D5E5F5G5H5J5K5A6B6C6D6E6F6G6H6J6K6A7B7C7D7E7F7G7H7J7K7A8B8C8D8E8F8G8H8J8K8A9B9C9D9E9F9G9H9J9K9A10B10C10D10E10F10G10H10J10K10E=4.20mm · Pitch e=0.40mmD=4.60mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.20mm × 4.60mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PI10I/OMultiplexed I/O & Peripheral Pin PI10 (General)
A2PH2I/OMultiplexed I/O & Peripheral Pin PH2 (General)
A3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (UART, PWM, CAN)
A4PH3BOOT0 -I/OMultiplexed I/O & Peripheral Pin PH3BOOT0 - (General)
A5PD7I/OMultiplexed I/O & Peripheral Pin PD7 (UART)
A6PD5I/OMultiplexed I/O & Peripheral Pin PD5 (UART)
A7PB4(NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4(NJTRST) (UART, SPI, I2C, SWD/JTAG)
A8PB3 (JTDO/TRACE SWO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO/TRACE SWO) (UART, SPI, PWM, SWD/JTAG)
A9PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)
A10PA14(JTCK/ SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14(JTCK/ SWCLK) (I2C, SWD/JTAG)
B1PI9I/OMultiplexed I/O & Peripheral Pin PI9 (CAN)
B2PI7I/OMultiplexed I/O & Peripheral Pin PI7 (PWM)
B3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (UART, I2C, CAN)
B4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
B6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (UART)
B7PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART, SPI)
B8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, SPI)
B9VSSGNDGround Reference Pin (VSS)
B10PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
C1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
C2VSSGNDGround Reference Pin (VSS)
C3PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
C4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
C5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, CAN)
C6PG14I/OMultiplexed I/O & Peripheral Pin PG14 (I2C)
C7PG13I/OMultiplexed I/O & Peripheral Pin PG13 (I2C)
C8PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
C9PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
C10VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
D1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, SPI, PWM)
D2PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, PWM)
D3VSSGNDGround Reference Pin (VSS)
D4PF2I/OMultiplexed I/O & Peripheral Pin PF2 (I2C)
D5PF1I/OMultiplexed I/O & Peripheral Pin PF1 (I2C)
D6PF0I/OMultiplexed I/O & Peripheral Pin PF0 (I2C)
D7PG12I/OMultiplexed I/O & Peripheral Pin PG12 (UART)
D8PG10I/OMultiplexed I/O & Peripheral Pin PG10 (UART)
D9PG9I/OMultiplexed I/O & Peripheral Pin PG9 (SPI)
D10PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
E1PC8I/OMultiplexed I/O & Peripheral Pin PC8 (PWM)
E2PC9I/OMultiplexed I/O & Peripheral Pin PC9 (I2C, PWM)
E3PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, RTC/CLK)
E4PF3I/OMultiplexed I/O & Peripheral Pin PF3 (ADC)
E5PG11I/OMultiplexed I/O & Peripheral Pin PG11 (General)
E6PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
E7PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
E8PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
E9PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
E10VSSGNDGround Reference Pin (VSS)
F1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F2PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
F3PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
F4PD15I/OMultiplexed I/O & Peripheral Pin PD15 (PWM)
F5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
F6PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
F7VSSGNDGround Reference Pin (VSS)
F8PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
F9PH1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)
F10PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
G1PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART, SPI)
G2PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
G3PG11I/OMultiplexed I/O & Peripheral Pin PG11 (UART)
G4PE13I/OMultiplexed I/O & Peripheral Pin PE13 (PWM)
G5PE12I/OMultiplexed I/O & Peripheral Pin PE12 (PWM)
G6PA5I/OMultiplexed I/O & Peripheral Pin PA5 (ADC, DAC, PWM)
G7VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
G8VREF -AnalogMultiplexed I/O & Peripheral Pin VREF - (General)
G9PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
G10PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
H1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (PWM, RTC/CLK)
H2PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, I2C, PWM)
H3PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
H4PE15I/OMultiplexed I/O & Peripheral Pin PE15 (SPI)
H5PE10I/OMultiplexed I/O & Peripheral Pin PE10 (PWM)
H6PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
H7PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
H8PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, I2C, ADC, PWM)
H9VSSAGNDGround Reference Pin (VSSA)
H10PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
J1PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, I2C)
J2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
J3PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C, PWM)
J4PE14I/OMultiplexed I/O & Peripheral Pin PE14 (SPI, PWM)
J5PE9I/OMultiplexed I/O & Peripheral Pin PE9 (PWM)
J6PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM)
J7PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
J8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J9PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
J10VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
K1PG15I/OMultiplexed I/O & Peripheral Pin PG15 (I2C)
K2VSSGNDGround Reference Pin (VSS)
K3PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, I2C, PWM)
K4PE11I/OMultiplexed I/O & Peripheral Pin PE11 (PWM)
K5PE8I/OMultiplexed I/O & Peripheral Pin PE8 (PWM)
K6PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
K7PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
K8PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
K9PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
K10VSSGNDGround Reference Pin (VSS)
PIN A1 PI10
I/O
Multiplexed I/O & Peripheral Pin PI10 (General)
Design note: Alt: EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L496VGY6PTR (ST · UFBGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L496VGY6PTR (UFBGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L496VGY6PTR (UFBGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L496VGY6PTR (UFBGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L496VGY6PTR (UFBGA-100) - 4. Package Dimensions (D×E×A)
UFBGA-100 · 4.20×4.60mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L496VGY6PTR (UFBGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L496VGY6PTR (UFBGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for STM32L496
P67 · p67_fig01EXACT PACKAGE
STM32L496VGY6PTR (UFBGA-100) — Figure 13. STM32L496Wx, external SMPS device, WLCSP115 ballout(1)(2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VDD PC11 PD2 VDD PG10 PG14 PB5 PB9 VSS VDD
Figure 13. STM32L496Wx, external SMPS device, WLCSP115 ballout(1)(2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VDD PC11 PD2 VDD PG10 PG14 PB5 PB9 VSS VDD
P67 · p67_fig02EXACT PACKAGE
STM32L496VGY6PTR (UFBGA-100) — Figure 14. STM32L496Vx LQFP100 pinout(1)
Figure 14. STM32L496Vx LQFP100 pinout(1)
P68 · p68_fig01EXACT PACKAGE
STM32L496VGY6PTR (UFBGA-100) — Figure 15. STM32L496Vx, external SMPS device, LQFP100 pinout(1)
Figure 15. STM32L496Vx, external SMPS device, LQFP100 pinout(1)
P69 · p69_fig01EXACT PACKAGE
STM32L496VGY6PTR (UFBGA-100) — Figure 16. STM32L496Vx WLCSP100L pinout(1)(2) 1 2 3 4 5 6 7 8 9 10 VDDUSB PA15 PD1 VDD PG10 VDDIO2 PB6 PB9 VSS VDD VSS PA14 PD0 PD4 PG9 PG12 PB5 PB8 PE2 PE3
Figure 16. STM32L496Vx WLCSP100L pinout(1)(2) 1 2 3 4 5 6 7 8 9 10 VDDUSB PA15 PD1 VDD PG10 VDDIO2 PB6 PB9 VSS VDD VSS PA14 PD0 PD4 PG9 PG12 PB5 PB8 PE2 PE3
P69 · p69_fig02EXACT PACKAGE
STM32L496VGY6PTR (UFBGA-100) — Figure 17. STM32L496Vx, external SMPS device, WLCSP100L pinout(1)(2)
Figure 17. STM32L496Vx, external SMPS device, WLCSP100L pinout(1)(2)
P1 · p01_fig01881×601px
STM32L496VGY6PTR (UFBGA-100) — • Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
• Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
P67 · p67_fig02P67
STM32L496VGY6PTR (UFBGA-100) — Datasheet Page 67 (p67_fig02)
Datasheet Page 67 (p67_fig02)
P121 · p121_fig011546×1933px
STM32L496VGY6PTR (UFBGA-100) — Figure 23. Power supply scheme VBAT
Figure 23. Power supply scheme VBAT
P121 · p121_fig01P121
STM32L496VGY6PTR (UFBGA-100) — Datasheet Page 121 (p121_fig01)
Datasheet Page 121 (p121_fig01)
P161 · p161_fig011546×702px
STM32L496VGY6PTR (UFBGA-100) — Figure 28. Typical application with an 8 MHz crystal
Figure 28. Typical application with an 8 MHz crystal
P162 · p162_fig011546×702px
STM32L496VGY6PTR (UFBGA-100) — Figure 29. Typical application with a 32.768 kHz crystal
Figure 29. Typical application with a 32.768 kHz crystal
P246 · p246_fig011546×1181px
STM32L496VGY6PTR (UFBGA-100) — Figure 65. UFBGA169 - Recommended footprint
Figure 65. UFBGA169 - Recommended footprint
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (STM32L496VGY6PTR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L496VGY6PTR (UFBGA-100) is a 100-pin embedded microcontroller unit (mcu) featuring a 4.60 × 4.20 × 0.53 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, DAC, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
80 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
70 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
4.60 × 4.20 × 0.53 mm (A1=0.18 mm)
Package family: WLCSP (UFBGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, ADC, DAC, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.60 × 4.20 mm
Height (A) & Pitch (e)IPC-7351B
A=0.53mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-100
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L496VGY6PTR (UFBGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L496VGY6PTR (UFBGA-100)?

Manufactured by ST, the STM32L496VGY6PTR is housed in a UFBGA-100 package with 100 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PI10: Multiplexed I/O & Peripheral Pin PI10 (General)), A2 (PH2: Multiplexed I/O & Peripheral Pin PH2 (General)), A3 (PB8: Multiplexed I/O & Peripheral Pin PB8 (UART, PWM, CAN)), A4 (PH3BOOT0 -: Multiplexed I/O & Peripheral Pin PH3BOOT0 - (General)), A5 (PD7: Multiplexed I/O & Peripheral Pin PD7 (UART)), A6 (PD5: Multiplexed I/O & Peripheral Pin PD5 (UART)).

What are the IPC-7351B PCB Footprint dimensions for STM32L496VGY6PTR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L496VGY6PTR (UFBGA-100) has a nominal body envelope of 4.20 × 4.60 mm, pitch e = 0.40 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L496VGY6PTR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L496VGY6PTR (ST, UFBGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32L496 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PI10Digital_IOSignal terminal PI10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI10. Supported peripheral buses: General.
A2PH2Digital_IOSignal terminal PH2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH2. Supported peripheral buses: General.
A3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: UART, PWM, CAN.
A4PH3BOOT0 -Digital_IOSignal terminal PH3BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3BOOT0 -. Supported peripheral buses: General.
A5PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: UART.
A6PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: UART.
A7PB4(NJTRST)Digital_IOSignal terminal PB4(NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG.
A8PB3 (JTDO/TRACE SWO)Digital_IOSignal terminal PB3 (JTDO/TRACE SWO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI, PWM, SWD/JTAG.
A9PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSSSPI3NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
A10PA14(JTCK/ SWCLK)Digital_IOSignal terminal PA14(JTCK/ SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14(JTCK/ SWCLK). Supported peripheral buses: I2C, SWD/JTAG.
B1PI9Digital_IOSignal terminal PI9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI9. Supported peripheral buses: CAN.
B2PI7Digital_IOSignal terminal PI7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI7. Supported peripheral buses: PWM.
B3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: UART, I2C, CAN.
B4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SDA. Supported peripheral buses: UART, I2C.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SCL. Supported peripheral buses: UART, I2C.
B6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: UART.
B7PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI.
B8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKDCMID5, SPI2_MISO. Supported peripheral buses: UART, SPI.
B9VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B10PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
C1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C3PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
C4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSISPI3MOSI. Supported peripheral buses: UART, SPI, CAN.
C6PG14Digital_IOSignal terminal PG14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG14. Supported peripheral buses: I2C.
C7PG13Digital_IOSignal terminal PG13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG13. Supported peripheral buses: I2C.
C8PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
C9PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
C10VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, PWM.
D2PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, PWM.
D3VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D4PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: I2C.
D5PF1Digital_IOSignal terminal PF1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: I2C.
D6PF0Digital_IOSignal terminal PF0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: I2C.
D7PG12Digital_IOSignal terminal PG12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG12. Supported peripheral buses: UART.
D8PG10Digital_IOSignal terminal PG10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG10. Supported peripheral buses: UART.
D9PG9Digital_IOSignal terminal PG9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCKUSART1TX. Supported peripheral buses: SPI.
D10PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
E1PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM.
E2PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: I2C, PWM.
E3PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, SPI, RTC/CLK.
E4PF3Digital_IOSignal terminal PF3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: ADC.
E5PG11Digital_IOSignal terminal PG11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG11. Supported peripheral buses: General.
E6PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
E7PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
E8PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
E9PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISOUSART3RX. Supported peripheral buses: UART, SPI.
E10VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F2PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
F3PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
F4PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: PWM.
F5PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: I2C, RTC/CLK.
F6PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSSPI3NSS. Supported peripheral buses: UART, SPI, ADC.
F7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F8PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI.
F9PH1-OSC_OUTDigital_IOSignal terminal PH1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1-OSC_OUT. Supported peripheral buses: RTC/CLK.
F10PH0-OSC_INDigital_IOSignal terminal PH0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK.
G1PD10Digital_IOSignal terminal PD10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: UART, SPI.
G2PD9Digital_IOSignal terminal PD9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: UART.
G3PG11Digital_IOSignal terminal PG11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG11. Supported peripheral buses: UART.
G4PE13Digital_IOSignal terminal PE13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE13. Supported peripheral buses: PWM.
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