![STM32H750VBT6TR (LQFP-100(14x14)) — Figure 6. TFBGA240+25 ballout [TFBGA-265]](/api/v1/assets/C405932/extracted/figures/p55_fig01.png)
![STM32H750VBT6TR (LQFP-100(14x14)) — Figure 120. TFBGA240+25 package outline [TFBGA-265]](/api/v1/assets/C405932/extracted/figures/p316_fig01.png)
![STM32H750VBT6TR (LQFP-100(14x14)) — Figure 121. TFBGA240+25 package recommended footprint [TFBGA-265]](/api/v1/assets/C405932/extracted/figures/p317_fig01.png)
LQFP-100(14x14) · 100P
Synchronized Pinout (Symbol / 2D / 3D) (100/100)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | 1 | I/O | Multiplexed I/O & Peripheral Pin 1 (UART, SPI) |
| 2 | 2 | I/O | Multiplexed I/O & Peripheral Pin 2 (General) |
| 3 | 3 | I/O | Multiplexed I/O & Peripheral Pin 3 (SPI) |
| 4 | 4 | I/O | Multiplexed I/O & Peripheral Pin 4 (SPI) |
| 5 | 5 | I/O | Multiplexed I/O & Peripheral Pin 5 (SPI) |
| 6 | 6 | I/O | Multiplexed I/O & Peripheral Pin 6 (General) |
| 7 | 7 | I/O | Multiplexed I/O & Peripheral Pin 7 (RTC/CLK) |
| 8 | 8 | I/O | Multiplexed I/O & Peripheral Pin 8 (RTC/CLK) |
| 9 | 9 | I/O | Multiplexed I/O & Peripheral Pin 9 (RTC/CLK) |
| 10 | - | I/O | Multiplexed I/O & Peripheral Pin - (I2C) |
| 11 | - | I/O | Multiplexed I/O & Peripheral Pin - (I2C) |
| 12 | - | I/O | Multiplexed I/O & Peripheral Pin - (I2C) |
| 13 | - | I/O | Multiplexed I/O & Peripheral Pin - (ADC) |
| 14 | - | I/O | Multiplexed I/O & Peripheral Pin - (ADC) |
| 15 | - | I/O | Multiplexed I/O & Peripheral Pin - (ADC) |
| 16 | 10 | I/O | Multiplexed I/O & Peripheral Pin 10 (General) |
| 17 | 11 | I/O | Multiplexed I/O & Peripheral Pin 11 (General) |
| 18 | - | I/O | Multiplexed I/O & Peripheral Pin - (ADC) |
| 19 | - | I/O | Multiplexed I/O & Peripheral Pin - (ADC) |
| 20 | - | I/O | Multiplexed I/O & Peripheral Pin - (UART, SPI, ADC) |
| 21 | - | I/O | Multiplexed I/O & Peripheral Pin - (ADC) |
| 22 | - | I/O | Multiplexed I/O & Peripheral Pin - (ADC) |
| 23 | 12 | I/O | Multiplexed I/O & Peripheral Pin 12 (RTC/CLK) |
| 24 | 13 | I/O | Multiplexed I/O & Peripheral Pin 13 (RTC/CLK) |
| 25 | 14 | I/O | Multiplexed I/O & Peripheral Pin 14 (General) |
| 26 | 15 | I/O | Multiplexed I/O & Peripheral Pin 15 (ADC) |
| 27 | 16 | I/O | Multiplexed I/O & Peripheral Pin 16 (SPI, ADC, RTC/CLK) |
| 28 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (General) |
| 29 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (General) |
| 30 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 31 | 19 | I/O | Multiplexed I/O & Peripheral Pin 19 (General) |
| 32 | 20 | I/O | Multiplexed I/O & Peripheral Pin 20 (General) |
| 33 | 21 | I/O | Multiplexed I/O & Peripheral Pin 21 (General) |
| 34 | 22 | I/O | Multiplexed I/O & Peripheral Pin 22 (UART, SPI, ADC, PWM) |
| 35 | 23 | I/O | Multiplexed I/O & Peripheral Pin 23 (UART, ADC, PWM) |
| 36 | 24 | I/O | Multiplexed I/O & Peripheral Pin 24 (UART, ADC, PWM) |
| 37 | 25 | I/O | Multiplexed I/O & Peripheral Pin 25 (UART, ADC, PWM) |
| 38 | 26 | I/O | Multiplexed I/O & Peripheral Pin 26 (General) |
| 39 | 27 | I/O | Multiplexed I/O & Peripheral Pin 27 (General) |
| 40 | 28 | I/O | Multiplexed I/O & Peripheral Pin 28 (UART, SPI, ADC, DAC) |
| 41 | 29 | I/O | Multiplexed I/O & Peripheral Pin 29 (SPI, ADC, DAC) |
| 42 | 30 | I/O | Multiplexed I/O & Peripheral Pin 30 (SPI, ADC) |
| 43 | 31 | I/O | Multiplexed I/O & Peripheral Pin 31 (SPI, ADC, PWM) |
| 44 | 32 | I/O | Multiplexed I/O & Peripheral Pin 32 (UART, ADC) |
| 45 | 33 | I/O | Multiplexed I/O & Peripheral Pin 33 (UART, ADC) |
| 46 | 34 | I/O | Multiplexed I/O & Peripheral Pin 34 (UART, ADC, PWM) |
| 47 | 35 | I/O | Multiplexed I/O & Peripheral Pin 35 (UART, ADC, PWM) |
| 48 | 36 | I/O | Multiplexed I/O & Peripheral Pin 36 (SPI, RTC/CLK) |
| 49 | - | I/O | Multiplexed I/O & Peripheral Pin - (SPI, ADC) |
| 50 | - | I/O | Multiplexed I/O & Peripheral Pin - (ADC) |
| 51 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 52 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 53 | - | I/O | Multiplexed I/O & Peripheral Pin - (ADC) |
| 54 | - | I/O | Multiplexed I/O & Peripheral Pin - (ADC) |
| 55 | - | I/O | Multiplexed I/O & Peripheral Pin - (I2C) |
| 56 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 57 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 58 | 37 | I/O | Multiplexed I/O & Peripheral Pin 37 (UART) |
| 59 | 38 | I/O | Multiplexed I/O & Peripheral Pin 38 (UART, PWM) |
| 60 | 39 | I/O | Multiplexed I/O & Peripheral Pin 39 (UART, PWM) |
| 61 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 62 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 63 | 40 | I/O | Multiplexed I/O & Peripheral Pin 40 (UART, PWM) |
| 64 | 41 | I/O | Multiplexed I/O & Peripheral Pin 41 (SPI, PWM) |
| 65 | 42 | I/O | Multiplexed I/O & Peripheral Pin 42 (SPI, PWM) |
| 66 | 43 | I/O | Multiplexed I/O & Peripheral Pin 43 (SPI, PWM) |
| 67 | 44 | I/O | Multiplexed I/O & Peripheral Pin 44 (PWM) |
| 68 | 45 | I/O | Multiplexed I/O & Peripheral Pin 45 (General) |
| 69 | 46 | I/O | Multiplexed I/O & Peripheral Pin 46 (SPI, PWM) |
| 70 | 47 | I/O | Multiplexed I/O & Peripheral Pin 47 (PWM) |
| 71 | 48 | I/O | Multiplexed I/O & Peripheral Pin 48 (General) |
| 72 | 50 | I/O | Multiplexed I/O & Peripheral Pin 50 (General) |
| 73 | VCAP | I/O | Multiplexed I/O & Peripheral Pin VCAP (General) |
| 74 | VSS | GND | Ground Reference Pin (VSS) |
| 75 | 53 | I/O | Multiplexed I/O & Peripheral Pin 53 (UART, SPI, PWM) |
| 76 | 54 | I/O | Multiplexed I/O & Peripheral Pin 54 (UART, SPI, RTC/CLK) |
| 77 | 55 | I/O | Multiplexed I/O & Peripheral Pin 55 (UART) |
| 78 | 56 | I/O | Multiplexed I/O & Peripheral Pin 56 (UART) |
| 79 | 57 | I/O | Multiplexed I/O & Peripheral Pin 57 (UART) |
| 80 | 58 | I/O | Multiplexed I/O & Peripheral Pin 58 (UART, SPI) |
| 81 | 59 | I/O | Multiplexed I/O & Peripheral Pin 59 (UART) |
| 82 | 60 | I/O | Multiplexed I/O & Peripheral Pin 60 (SPI, I2C) |
| 83 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 84 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 85 | 61 | I/O | Multiplexed I/O & Peripheral Pin 61 (UART) |
| 86 | 62 | I/O | Multiplexed I/O & Peripheral Pin 62 (UART) |
| 87 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 88 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 89 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 90 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 91 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 92 | - | I/O | Multiplexed I/O & Peripheral Pin - (UART) |
| 93 | - | I/O | Multiplexed I/O & Peripheral Pin - (UART) |
| 94 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 95 | - | I/O | Multiplexed I/O & Peripheral Pin - (General) |
| 96 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (General) |
| 97 | PE0 | I/O | Multiplexed I/O & Peripheral Pin PE0 (General) |
| 98 | PE1 | I/O | Multiplexed I/O & Peripheral Pin PE1 (General) |
| 99 | VSS | GND | Ground Reference Pin (VSS) |
| 100 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
PIN 1 1
I/OMultiplexed I/O & Peripheral Pin 1 (UART, SPI)
Design note: PE2 | Alt: TRACECLK SAI1 CK1 ,_ , SPI4 SCK_SAI1MCLKA ,__ , SAI4_MCLKA_ , QUADSPI BK1_IO2SAI4CK1_ ,_ , ETH MII_TXD3FMCA23_ ,_ , EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for STM32H750
P53 · p53_fig01EXACT PACKAGE
P95 · p95_fig01EXACT PACKAGE
P201 · p201_fig01EXACT PACKAGE
P312 · p312_fig01EXACT PACKAGE
P314 · p314_fig01EXACT PACKAGE
P1 · p01_fig01881×669px
P318 · p318_fig01All Packages in PDF
P322 · p322_fig01All Packages in PDF
P55 · p55_fig01EXACT PACKAGE
P316 · p316_fig01EXACT PACKAGE
P317 · p317_fig01EXACT PACKAGE
Technical Specifications & Part Details (STM32H750VBT6TR)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32H750VBT6TR (LQFP-100(14x14)) is a 100-pin embedded microcontroller unit (mcu) featuring a 14.00 × 14.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, DAC, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
480MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
61 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-100(14x14))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, DAC, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol100 auto-grouped pins
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32H750 (4)
LQFP-100(14x14) · 100P
TFBGA-265 · 265P
TFBGA-265 · 265P
Mechanical Dimensions & Land Pattern (LQFP-100(14x14))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.20 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-100(14x14) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32H750VBT6TR (LQFP-100(14x14))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32H750VBT6TR (LQFP-100(14x14))?
Manufactured by ST, the STM32H750VBT6TR is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch. Key pins include: 1 (1: Multiplexed I/O & Peripheral Pin 1 (UART, SPI)), 2 (2: Multiplexed I/O & Peripheral Pin 2 (General)), 3 (3: Multiplexed I/O & Peripheral Pin 3 (SPI)), 4 (4: Multiplexed I/O & Peripheral Pin 4 (SPI)), 5 (5: Multiplexed I/O & Peripheral Pin 5 (SPI)), 6 (6: Multiplexed I/O & Peripheral Pin 6 (General)).
What are the IPC-7351B PCB Footprint dimensions for STM32H750VBT6TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H750VBT6TR (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H750VBT6TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H750VBT6TR (ST, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (100 pins) & STM32H750 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | 1 | Digital_IO | Signal terminal 1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCK_SAI1MCLKA. Supported peripheral buses: UART, SPI. |
| 2 | 2 | Digital_IO | Signal terminal 2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 2. Supported peripheral buses: General. |
| 3 | 3 | Digital_IO | Signal terminal 3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS_SAI1FSA. Supported peripheral buses: SPI. |
| 4 | 4 | Digital_IO | Signal terminal 4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO_SAI1SCKA. Supported peripheral buses: SPI. |
| 5 | 5 | Digital_IO | Signal terminal 5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MOSI_SAI1SDA. Supported peripheral buses: SPI. |
| 6 | 6 | Digital_IO | Signal terminal 6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 6. Supported peripheral buses: General. |
| 7 | 7 | Digital_IO | Signal terminal 7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 7. Supported peripheral buses: RTC/CLK. |
| 8 | 8 | Digital_IO | Signal terminal 8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 8. Supported peripheral buses: RTC/CLK. |
| 9 | 9 | Digital_IO | Signal terminal 9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 9. Supported peripheral buses: RTC/CLK. |
| 10 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: I2C. |
| 11 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: I2C. |
| 12 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: I2C. |
| 13 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: ADC. |
| 14 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: ADC. |
| 15 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: ADC. |
| 16 | 10 | Digital_IO | Signal terminal 10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 10. Supported peripheral buses: General. |
| 17 | 11 | Digital_IO | Signal terminal 11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 11. Supported peripheral buses: General. |
| 18 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: ADC. |
| 19 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: ADC. |
| 20 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: UART, SPI, ADC. |
| 21 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: ADC. |
| 22 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: ADC. |
| 23 | 12 | Digital_IO | Signal terminal 12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 12. Supported peripheral buses: RTC/CLK. |
| 24 | 13 | Digital_IO | Signal terminal 13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 13. Supported peripheral buses: RTC/CLK. |
| 25 | 14 | Digital_IO | Signal terminal 14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 14. Supported peripheral buses: General. |
| 26 | 15 | Digital_IO | Signal terminal 15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 15. Supported peripheral buses: ADC. |
| 27 | 16 | Digital_IO | Signal terminal 16 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC, RTC/CLK. |
| 28 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General. |
| 29 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General. |
| 30 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: -. Supported peripheral buses: General. |
| 31 | 19 | Digital_IO | Signal terminal 19 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 19. Supported peripheral buses: General. |
| 32 | 20 | Digital_IO | Signal terminal 20 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 20. Supported peripheral buses: General. |
| 33 | 21 | Digital_IO | Signal terminal 21 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 21. Supported peripheral buses: General. |
| 34 | 22 | Digital_IO | Signal terminal 22 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 22. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 35 | 23 | Digital_IO | Signal terminal 23 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 23. Supported peripheral buses: UART, ADC, PWM. |
| 36 | 24 | Digital_IO | Signal terminal 24 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 24. Supported peripheral buses: UART, ADC, PWM. |
| 37 | 25 | Digital_IO | Signal terminal 25 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 25. Supported peripheral buses: UART, ADC, PWM. |
| 38 | 26 | Digital_IO | Signal terminal 26 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 26. Supported peripheral buses: General. |
| 39 | 27 | Digital_IO | Signal terminal 27 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 27. Supported peripheral buses: General. |
| 40 | 28 | Digital_IO | Signal terminal 28 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC, DAC. |
| 41 | 29 | Digital_IO | Signal terminal 29 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK, SPI6_SCK. Supported peripheral buses: SPI, ADC, DAC. |
| 42 | 30 | Digital_IO | Signal terminal 30 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI6_MISOTIM13CH1. Supported peripheral buses: SPI, ADC. |
| 43 | 31 | Digital_IO | Signal terminal 31 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI, SPI6_MOSITIM14CH1. Supported peripheral buses: SPI, ADC, PWM. |
| 44 | 32 | Digital_IO | Signal terminal 32 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 32. Supported peripheral buses: UART, ADC. |
| 45 | 33 | Digital_IO | Signal terminal 33 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 33. Supported peripheral buses: UART, ADC. |
| 46 | 34 | Digital_IO | Signal terminal 34 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 34. Supported peripheral buses: UART, ADC, PWM. |
| 47 | 35 | Digital_IO | Signal terminal 35 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 35. Supported peripheral buses: UART, ADC, PWM. |
| 48 | 36 | Digital_IO | Signal terminal 36 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI, RTC/CLK. |
| 49 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI5_MOSI_SAI2SDB. Supported peripheral buses: SPI, ADC. |
| 50 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: ADC. |
| 51 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: -. Supported peripheral buses: General. |
| 52 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: -. Supported peripheral buses: General. |
| 53 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: ADC. |
| 54 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: ADC. |
| 55 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: I2C. |
| 56 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: -. Supported peripheral buses: General. |
| 57 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: -. Supported peripheral buses: General. |
| 58 | 37 | Digital_IO | Signal terminal 37 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 37. Supported peripheral buses: UART. |
| 59 | 38 | Digital_IO | Signal terminal 38 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 38. Supported peripheral buses: UART, PWM. |
| 60 | 39 | Digital_IO | Signal terminal 39 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 39. Supported peripheral buses: UART, PWM. |
| 61 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: -. Supported peripheral buses: General. |
| 62 | - | Digital_IO | Signal terminal - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: -. Supported peripheral buses: General. |
| 63 | 40 | Digital_IO | Signal terminal 40 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: 40. Supported peripheral buses: UART, PWM. |
| 64 | 41 | Digital_IO | Signal terminal 41 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS_SAI2SDB. Supported peripheral buses: SPI, PWM. |