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ESP8684H2 (QFN-24(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP8684H2

ESPRESSIFID: C2922574QFN-24(4x4) · 25 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP8684H2 (QFN-24(4x4))1ANT2VDDA3P33VDDA3P34GPIO05GPIO16GPIO27CHIP_EN8GPIO39MTMS10MTDI11VDD3P3_RTC12MTCK13MTDO25GND24VDDA23XTAL_P22XTAL_N21VDDA20U0TXD19U0RXD18GPIO1817VDD3P3_CPU16GPIO1015GPIO914GPIO8Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (25/25)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
2VDDA3P3PowerPower Supply Input (VDDA3P3 — 3.3V / 5.0V Standard Logic)
3VDDA3P3PowerPower Supply Input (VDDA3P3 — 3.3V / 5.0V Standard Logic)
4GPIO0I/OMultiplexed I/O & Peripheral Pin GPIO0 (General)
5GPIO1I/OMultiplexed I/O & Peripheral Pin GPIO1 (General)
6GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (General)
7CHIP_ENI/OMultiplexed I/O & Peripheral Pin CHIP_EN (General)
8GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (General)
9MTMSI/OMultiplexed I/O & Peripheral Pin MTMS (SWD/JTAG)
10MTDII/OMultiplexed I/O & Peripheral Pin MTDI (SWD/JTAG)
11VDD3P3_RTCPowerPower Supply Input (VDD3P3_RTC — 3.3V / 5.0V Standard Logic)
12MTCKI/OMultiplexed I/O & Peripheral Pin MTCK (SPI, SWD/JTAG)
13MTDOI/OMultiplexed I/O & Peripheral Pin MTDO (SPI, SWD/JTAG)
14GPIO8I/OMultiplexed I/O & Peripheral Pin GPIO8 (General)
15GPIO9I/OMultiplexed I/O & Peripheral Pin GPIO9 (General)
16GPIO10I/OMultiplexed I/O & Peripheral Pin GPIO10 (SPI)
17VDD3P3_CPUPowerPower Supply Input (VDD3P3_CPU — 3.3V / 5.0V Standard Logic)
18GPIO18I/OMultiplexed I/O & Peripheral Pin GPIO18 (General)
19U0RXDI/OMultiplexed I/O & Peripheral Pin U0RXD (UART)
20U0TXDI/OMultiplexed I/O & Peripheral Pin U0TXD (UART)
21VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
22XTAL_NI/OMultiplexed I/O & Peripheral Pin XTAL_N (RTC/CLK)
23XTAL_PI/OMultiplexed I/O & Peripheral Pin XTAL_P (RTC/CLK)
24VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
25GNDGNDGround Reference Pin (GND)
PIN 1 ANT
I/O
Multiplexed I/O & Peripheral Pin ANT (General)
Design note: RFinputandoutput
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP8684H2 (ESPRESSIF · QFN-24(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP8684H2 (QFN-24(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP8684H2 (QFN-24(4x4)) - 2. Standard Pinout (Top View)
True package pinout (25 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP8684H2 (QFN-24(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP8684H2 (QFN-24(4x4)) - 4. Package Dimensions (D×E×A)
QFN-24(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP8684H2 (QFN-24(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (25 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP8684H2 (QFN-24(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for ESP8684
P36 · p36_fig01EXACT PACKAGE
ESP8684H2 (QFN-24(4x4)) — Figure 8: QFN24 (4×4 mm) Package
Figure 8: QFN24 (4×4 mm) Package
P1 · p01_fig01726×314px
ESP8684H2 (QFN-24(4x4)) — www.espressif.com
www.espressif.com
P2 · p02_fig011989×1742px
ESP8684H2 (QFN-24(4x4)) — Figure 1: Functional block diagram of ESP8684
Figure 1: Functional block diagram of ESP8684
P10 · p10_fig011217×1144px
ESP8684H2 (QFN-24(4x4)) — Figure 3: ESP8684 Pin Layout (Top View)
Figure 3: ESP8684 Pin Layout (Top View)
P10 · p10_fig02600×195px
ESP8684H2 (QFN-24(4x4)) — 4
4
P10 · p10_fig01P10
ESP8684H2 (QFN-24(4x4)) — Datasheet Page 10 (p10_fig01)
Datasheet Page 10 (p10_fig01)

Technical Specifications & Part Details (ESP8684H2)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:ESP8684H2 (QFN-24(4x4)) is a 24-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 1.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 40 °C to 125 °C with integrated Wi-Fi, Bluetooth / BLE, UART, SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
40 °C to 125 °C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
500 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-24(4x4))
Pin Count & Lead PitchN / e
24 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, UART, SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (GPIO0, MTDI, MTDO): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol25 auto-grouped pins
OK
IPC-7351B Land Pattern25 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.56×2.56mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-24(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
25P / 25Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-24(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ESP8684H2 (QFN-24(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP8684H2 (QFN-24(4x4))?

Manufactured by ESPRESSIF, the ESP8684H2 is housed in a QFN-24(4x4) package with 25 pins and a 0.50 mm lead pitch. Key pins include: 1 (ANT: Multiplexed I/O & Peripheral Pin ANT (General)), 2 (VDDA3P3: Power Supply Input (VDDA3P3 — 3.3V / 5.0V Standard Logic)), 3 (VDDA3P3: Power Supply Input (VDDA3P3 — 3.3V / 5.0V Standard Logic)), 4 (GPIO0: Multiplexed I/O & Peripheral Pin GPIO0 (General)), 5 (GPIO1: Multiplexed I/O & Peripheral Pin GPIO1 (General)), 6 (GPIO2: Multiplexed I/O & Peripheral Pin GPIO2 (General)).

What are the IPC-7351B PCB Footprint dimensions for ESP8684H2?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP8684H2 (QFN-24(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 25 copper pads plus a central exposed thermal pad (EPAD) of 2.56 × 2.56 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP8684H2?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP8684H2 (ESPRESSIF, QFN-24(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (25 pins) & ESP8684 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
2VDDA3P3Power_InPrimary positive power supply input (VDDA3P3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3VDDA3P3Power_InPrimary positive power supply input (VDDA3P3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4GPIO0Digital_IOSignal terminal GPIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO0. Supported peripheral buses: General.
5GPIO1Digital_IOSignal terminal GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: General.
6GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
7CHIP_ENDigital_IOSignal terminal CHIP_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CHIP_EN. Supported peripheral buses: General.
8GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General.
9MTMSDigital_IOSignal terminal MTMS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MTMS. Supported peripheral buses: SWD/JTAG.
10MTDIDigital_IOSignal terminal MTDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MTDI. Supported peripheral buses: SWD/JTAG.
11VDD3P3_RTCPower_InPrimary positive power supply input (VDD3P3_RTC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12MTCKDigital_IOSignal terminal MTCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO6, FSPICLK. Supported peripheral buses: SPI, SWD/JTAG.
13MTDODigital_IOSignal terminal MTDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO7, FSPID. Supported peripheral buses: SPI, SWD/JTAG.
14GPIO8Digital_IOSignal terminal GPIO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General.
15GPIO9Digital_IOSignal terminal GPIO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General.
16GPIO10Digital_IOSignal terminal GPIO10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FSPICS0. Supported peripheral buses: SPI.
17VDD3P3_CPUPower_InPrimary positive power supply input (VDD3P3_CPU) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
18GPIO18Digital_IOSignal terminal GPIO18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO18. Supported peripheral buses: General.
19U0RXDDigital_IOSignal terminal U0RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO19. Supported peripheral buses: UART.
20U0TXDDigital_IOSignal terminal U0TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO20. Supported peripheral buses: UART.
21VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22XTAL_NDigital_IOSignal terminal XTAL_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_N. Supported peripheral buses: RTC/CLK.
23XTAL_PDigital_IOSignal terminal XTAL_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_P. Supported peripheral buses: RTC/CLK.
24VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
25GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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