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CH582M (QFN-48-EP(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH582M

WCHID: C2920766QFN-48-EP(5x5) · 49 Pins · Pitch 0.35mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH582M (QFN-48-EP(5x5))1VDCID2VSW3VIO33/VDD334PA7/TXD2/PWM5PA8/RXD1/AIN6PA9/TMR0/TXD7PB98PB89PB1710PB1611PB15/TCK/MIS12IO713IO1514IO1615PB11/UD+/TMR16PB10/UD-/TMR17PB7/TXD0/PWM18PB6/RTS/PWM819PB5/DTR20PB4/RXD0/PWM21PB3/DCD/PWM922PB2/RI/PWM8_23PB1/DSR/PWM724PB0/CTS/PWM625IO1449EP48PA10/X32KI/T47PA11/X32KO/T46PA12/SCS/PWM45PA13/SCK0/PW44PA14/MOSI/TX43PA15/MISO/RX42PA3/AIN641PA2/TMR3_/AI40PA1/AIN839PA0/AIN938PA6/RXD2/PWM37PA5/TXD3/AIN36PA4/RXD3/AIN35VDCIA34ANT33VINTA32X32MI31X32MO30PB1829PB1928PB20/SDA_/RX27PB21/SCL_/TX26PB22/TMR3/RXGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910252627282930313233342423222120191817161514131211484746454443424140393837363549E=5.00mm · Pitch e=0.35mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDCIDI/OMultiplexed I/O & Peripheral Pin VDCID (General)
2VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
3VIO33/VDD33PowerPower Supply Input (VIO33/VDD33 — 3.3V / 5.0V Standard Logic)
4PA7/TXD2/PWM5_/AIN11I/OMultiplexed I/O & Peripheral Pin PA7/TXD2/PWM5_/AIN11 (UART, ADC, PWM)
5PA8/RXD1/AIN12I/OMultiplexed I/O & Peripheral Pin PA8/RXD1/AIN12 (UART, ADC)
6PA9/TMR0/TXD1/AIN13I/OMultiplexed I/O & Peripheral Pin PA9/TMR0/TXD1/AIN13 (UART, ADC)
7PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
8PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
9PB17I/OMultiplexed I/O & Peripheral Pin PB17 (General)
10PB16I/OMultiplexed I/O & Peripheral Pin PB16 (General)
11PB15/TCK/MISO_/DTR_I/OMultiplexed I/O & Peripheral Pin PB15/TCK/MISO_/DTR_ (UART, SPI)
12IO7I/OGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13IO15I/OGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14IO16I/OGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15PB11/UD+/TMR2_I/OMultiplexed I/O & Peripheral Pin PB11/UD+/TMR2_ (USB)
16PB10/UD-/TMR1_I/OMultiplexed I/O & Peripheral Pin PB10/UD-/TMR1_ (USB)
17PB7/TXD0/PWM9I/OMultiplexed I/O & Peripheral Pin PB7/TXD0/PWM9 (UART, PWM)
18PB6/RTS/PWM8I/OMultiplexed I/O & Peripheral Pin PB6/RTS/PWM8 (UART, PWM)
19PB5/DTRI/OMultiplexed I/O & Peripheral Pin PB5/DTR (UART)
20PB4/RXD0/PWM7I/OMultiplexed I/O & Peripheral Pin PB4/RXD0/PWM7 (UART, PWM)
21PB3/DCD/PWM9_I/OMultiplexed I/O & Peripheral Pin PB3/DCD/PWM9_ (PWM)
22PB2/RI/PWM8_I/OMultiplexed I/O & Peripheral Pin PB2/RI/PWM8_ (PWM)
23PB1/DSR/PWM7_I/OMultiplexed I/O & Peripheral Pin PB1/DSR/PWM7_ (UART, PWM)
24PB0/CTS/PWM6I/OMultiplexed I/O & Peripheral Pin PB0/CTS/PWM6 (UART, PWM)
25IO14I/OGPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26PB22/TMR3/RXD2_I/OMultiplexed I/O & Peripheral Pin PB22/TMR3/RXD2_ (UART)
27PB21/SCL_/TXD3_I/OMultiplexed I/O & Peripheral Pin PB21/SCL_/TXD3_ (UART, I2C)
28PB20/SDA_/RXD3_I/OMultiplexed I/O & Peripheral Pin PB20/SDA_/RXD3_ (UART, I2C)
29PB19I/OMultiplexed I/O & Peripheral Pin PB19 (General)
30PB18I/OMultiplexed I/O & Peripheral Pin PB18 (General)
31X32MOI/OMultiplexed I/O & Peripheral Pin X32MO (General)
32X32MII/OMultiplexed I/O & Peripheral Pin X32MI (General)
33VINTAPowerPower Supply Input (VINTA — 3.3V / 5.0V Standard Logic)
34ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
35VDCIAI/OMultiplexed I/O & Peripheral Pin VDCIA (General)
36PA4/RXD3/AIN0I/OMultiplexed I/O & Peripheral Pin PA4/RXD3/AIN0 (UART, ADC)
37PA5/TXD3/AIN1I/OMultiplexed I/O & Peripheral Pin PA5/TXD3/AIN1 (UART, ADC)
38PA6/RXD2/PWM4_/AIN10I/OMultiplexed I/O & Peripheral Pin PA6/RXD2/PWM4_/AIN10 (UART, ADC, PWM)
39PA0/AIN9I/OMultiplexed I/O & Peripheral Pin PA0/AIN9 (ADC)
40PA1/AIN8I/OMultiplexed I/O & Peripheral Pin PA1/AIN8 (ADC)
41PA2/TMR3_/AIN7I/OMultiplexed I/O & Peripheral Pin PA2/TMR3_/AIN7 (ADC)
42PA3/AIN6I/OMultiplexed I/O & Peripheral Pin PA3/AIN6 (ADC)
43PA15/MISO/RXD0_/AIN5I/OMultiplexed I/O & Peripheral Pin PA15/MISO/RXD0_/AIN5 (UART, SPI, ADC)
44PA14/MOSI/TXD0_/AIN4I/OMultiplexed I/O & Peripheral Pin PA14/MOSI/TXD0_/AIN4 (UART, SPI, ADC)
45PA13/SCK0/PWM5/AIN3I/OMultiplexed I/O & Peripheral Pin PA13/SCK0/PWM5/AIN3 (SPI, ADC, PWM)
46PA12/SCS/PWM4/AIN2I/OMultiplexed I/O & Peripheral Pin PA12/SCS/PWM4/AIN2 (ADC, PWM)
47PA11/X32KO/TMR2I/OMultiplexed I/O & Peripheral Pin PA11/X32KO/TMR2 (General)
48PA10/X32KI/TMR1I/OMultiplexed I/O & Peripheral Pin PA10/X32KI/TMR1 (General)
49EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VDCID
I/O
Multiplexed I/O & Peripheral Pin VDCID (General)
Design note: Signal terminal VDCID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCID. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH582M (WCH · QFN-48-EP(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH582M (QFN-48-EP(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH582M (QFN-48-EP(5x5)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH582M (QFN-48-EP(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH582M (QFN-48-EP(5x5)) - 4. Package Dimensions (D×E×A)
QFN-48-EP(5x5) · 5.00×5.00mm · Pitch 0.35mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH582M (QFN-48-EP(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH582M (QFN-48-EP(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH582 / CH583
P3 · p03_fig01EXACT PACKAGE
CH582M (QFN-48-EP(5x5)) — 图1-1 CH582M/CH583M(QFN48)和CH582F(QFN28)封装引脚排列
图1-1 CH582M/CH583M(QFN48)和CH582F(QFN28)封装引脚排列
P111 · p111_fig01EXACT PACKAGE
CH582M (QFN-48-EP(5x5)) — QFN48 5*5mm 0.35mm 13.8mil 方形无引线48 脚 CH583M QFN48 5*5mm 0.35mm 13.8mil 方形无引线48 脚 CH582M QFN28 4*4mm 0.4mm 15.7mil 方形无引线28 脚 CH582F 说明：尺寸标注的单位是mm（毫米），引脚中心间距是标称值，除此之外的尺寸误差不大于±0.2mm。 QFN48_5X5
QFN48 5*5mm 0.35mm 13.8mil 方形无引线48 脚 CH583M QFN48 5*5mm 0.35mm 13.8mil 方形无引线48 脚 CH582M QFN28 4*4mm 0.4mm 15.7mil 方形无引线28 脚 CH582F 说明：尺寸标注的单位是mm（毫米），引脚中心间距是标称值，除此之外的尺寸误差不大于±0.2mm。 QFN48_5X5
P1 · p01_fig01288×163px
CH582M (QFN-48-EP(5x5)) — CH583 是集成BLE 无线通讯的RISC-V MCU 微控制器（SoC）。片上集成2Mbps 低功耗蓝牙BLE 通 讯模块、2 个全速USB 主机和设备控制器及收发器、2 个SPI、4 个串口、14 路ADC、触摸按键检测模 块、RTC 等丰富的外设资源。 功能
CH583 是集成BLE 无线通讯的RISC-V MCU 微控制器（SoC）。片上集成2Mbps 低功耗蓝牙BLE 通 讯模块、2 个全速USB 主机和设备控制器及收发器、2 个SPI、4 个串口、14 路ADC、触摸按键检测模 块、RTC 等丰富的外设资源。 功能
P3 · p03_fig01P3
CH582M (QFN-48-EP(5x5)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P67 · p67_fig011713×2650px
CH582M (QFN-48-EP(5x5)) — V1.9 67 WCH
V1.9 67 WCH
P68 · p68_fig011713×2645px
CH582M (QFN-48-EP(5x5)) — V1.9 68 WCH
V1.9 68 WCH
P69 · p69_fig011713×802px
CH582M (QFN-48-EP(5x5)) — CH583/CH582 数据手册 https://wch.cn
CH583/CH582 数据手册 https://wch.cn
P69 · p69_fig021713×989px
CH582M (QFN-48-EP(5x5)) — SPI 支持模式0 和模式3 两种传输格式，通过设置R8_SPIx_CTRL_MOD 的RB_SPI_MST_SCK_MOD 进 行选择。总是在SCK 上升沿采样串行数据输入，在下降沿输出串行数据。
SPI 支持模式0 和模式3 两种传输格式，通过设置R8_SPIx_CTRL_MOD 的RB_SPI_MST_SCK_MOD 进 行选择。总是在SCK 上升沿采样串行数据输入，在下降沿输出串行数据。

Technical Specifications & Part Details (CH582M)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH582M (QFN-48-EP(5x5)) is a 48-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, SPI, I2C, ADC, PWM, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-48-EP(5x5))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, SPI, I2C, ADC, PWM, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.35mm
OK
IPC-7525 60% Solder PasteEPAD 3.70×3.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-48-EP(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.35mm
Pad Size (W × L)Level B
0.16 × 0.75 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-48-EP(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH582M (QFN-48-EP(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH582M (QFN-48-EP(5x5))?

Manufactured by WCH, the CH582M is housed in a QFN-48-EP(5x5) package with 49 pins and a 0.35 mm lead pitch. Key pins include: 1 (VDCID: Multiplexed I/O & Peripheral Pin VDCID (General)), 2 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 3 (VIO33/VDD33: Power Supply Input (VIO33/VDD33 — 3.3V / 5.0V Standard Logic)), 4 (PA7/TXD2/PWM5_/AIN11: Multiplexed I/O & Peripheral Pin PA7/TXD2/PWM5_/AIN11 (UART, ADC, PWM)), 5 (PA8/RXD1/AIN12: Multiplexed I/O & Peripheral Pin PA8/RXD1/AIN12 (UART, ADC)), 6 (PA9/TMR0/TXD1/AIN13: Multiplexed I/O & Peripheral Pin PA9/TMR0/TXD1/AIN13 (UART, ADC)).

What are the IPC-7351B PCB Footprint dimensions for CH582M?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH582M (QFN-48-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.35 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 3.70 × 3.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH582M?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH582M (WCH, QFN-48-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & CH582 / CH583 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDCIDDigital_IOSignal terminal VDCID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCID. Supported peripheral buses: General.
2VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
3VIO33/VDD33Power_InPrimary positive power supply input (VIO33/VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4PA7/TXD2/PWM5_/AIN11Digital_IOSignal terminal PA7/TXD2/PWM5_/AIN11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/TXD2/PWM5_/AIN11. Supported peripheral buses: UART, ADC, PWM.
5PA8/RXD1/AIN12Digital_IOSignal terminal PA8/RXD1/AIN12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8/RXD1/AIN12. Supported peripheral buses: UART, ADC.
6PA9/TMR0/TXD1/AIN13Digital_IOSignal terminal PA9/TMR0/TXD1/AIN13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9/TMR0/TXD1/AIN13. Supported peripheral buses: UART, ADC.
7PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
8PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
9PB17Digital_IOSignal terminal PB17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB17. Supported peripheral buses: General.
10PB16Digital_IOSignal terminal PB16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB16. Supported peripheral buses: General.
11PB15/TCK/MISO_/DTR_Digital_IOSignal terminal PB15/TCK/MISO_/DTR_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15/TCK/MISO_/DTR_. Supported peripheral buses: UART, SPI.
12IO7Digital_IOGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13IO15Digital_IOGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14IO16Digital_IOGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15PB11/UD+/TMR2_Digital_IOSignal terminal PB11/UD+/TMR2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11/UD+/TMR2_. Supported peripheral buses: USB.
16PB10/UD-/TMR1_Digital_IOSignal terminal PB10/UD-/TMR1_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10/UD-/TMR1_. Supported peripheral buses: USB.
17PB7/TXD0/PWM9Digital_IOSignal terminal PB7/TXD0/PWM9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/TXD0/PWM9. Supported peripheral buses: UART, PWM.
18PB6/RTS/PWM8Digital_IOSignal terminal PB6/RTS/PWM8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6/RTS/PWM8. Supported peripheral buses: UART, PWM.
19PB5/DTRDigital_IOSignal terminal PB5/DTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5/DTR. Supported peripheral buses: UART.
20PB4/RXD0/PWM7Digital_IOSignal terminal PB4/RXD0/PWM7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4/RXD0/PWM7. Supported peripheral buses: UART, PWM.
21PB3/DCD/PWM9_Digital_IOSignal terminal PB3/DCD/PWM9_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3/DCD/PWM9_. Supported peripheral buses: PWM.
22PB2/RI/PWM8_Digital_IOSignal terminal PB2/RI/PWM8_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2/RI/PWM8_. Supported peripheral buses: PWM.
23PB1/DSR/PWM7_Digital_IOSignal terminal PB1/DSR/PWM7_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/DSR/PWM7_. Supported peripheral buses: UART, PWM.
24PB0/CTS/PWM6Digital_IOSignal terminal PB0/CTS/PWM6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/CTS/PWM6. Supported peripheral buses: UART, PWM.
25IO14Digital_IOGPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26PB22/TMR3/RXD2_Digital_IOSignal terminal PB22/TMR3/RXD2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB22/TMR3/RXD2_. Supported peripheral buses: UART.
27PB21/SCL_/TXD3_Digital_IOSignal terminal PB21/SCL_/TXD3_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB21/SCL_/TXD3_. Supported peripheral buses: UART, I2C.
28PB20/SDA_/RXD3_Digital_IOSignal terminal PB20/SDA_/RXD3_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB20/SDA_/RXD3_. Supported peripheral buses: UART, I2C.
29PB19Digital_IOSignal terminal PB19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB19. Supported peripheral buses: General.
30PB18Digital_IOSignal terminal PB18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB18. Supported peripheral buses: General.
31X32MODigital_IOSignal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General.
32X32MIDigital_IOSignal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General.
33VINTAPower_InPrimary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
34ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
35VDCIADigital_IOSignal terminal VDCIA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCIA. Supported peripheral buses: General.
36PA4/RXD3/AIN0Digital_IOSignal terminal PA4/RXD3/AIN0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/RXD3/AIN0. Supported peripheral buses: UART, ADC.
37PA5/TXD3/AIN1Digital_IOSignal terminal PA5/TXD3/AIN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/TXD3/AIN1. Supported peripheral buses: UART, ADC.
38PA6/RXD2/PWM4_/AIN10Digital_IOSignal terminal PA6/RXD2/PWM4_/AIN10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/RXD2/PWM4_/AIN10. Supported peripheral buses: UART, ADC, PWM.
39PA0/AIN9AnalogSignal terminal PA0/AIN9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0/AIN9. Supported peripheral buses: ADC.
40PA1/AIN8AnalogSignal terminal PA1/AIN8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/AIN8. Supported peripheral buses: ADC.
41PA2/TMR3_/AIN7AnalogSignal terminal PA2/TMR3_/AIN7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2/TMR3_/AIN7. Supported peripheral buses: ADC.
42PA3/AIN6AnalogSignal terminal PA3/AIN6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3/AIN6. Supported peripheral buses: ADC.
43PA15/MISO/RXD0_/AIN5Digital_IOSignal terminal PA15/MISO/RXD0_/AIN5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15/MISO/RXD0_/AIN5. Supported peripheral buses: UART, SPI, ADC.
44PA14/MOSI/TXD0_/AIN4Digital_IOSignal terminal PA14/MOSI/TXD0_/AIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/MOSI/TXD0_/AIN4. Supported peripheral buses: UART, SPI, ADC.
45PA13/SCK0/PWM5/AIN3Digital_IOSignal terminal PA13/SCK0/PWM5/AIN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13/SCK0/PWM5/AIN3. Supported peripheral buses: SPI, ADC, PWM.
46PA12/SCS/PWM4/AIN2AnalogSignal terminal PA12/SCS/PWM4/AIN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/SCS/PWM4/AIN2. Supported peripheral buses: ADC, PWM.
47PA11/X32KO/TMR2Digital_IOSignal terminal PA11/X32KO/TMR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/X32KO/TMR2. Supported peripheral buses: General.
48PA10/X32KI/TMR1Digital_IOSignal terminal PA10/X32KI/TMR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10/X32KI/TMR1. Supported peripheral buses: General.
49EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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