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C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3) — Symbol, Footprint IPC-7351B & 3D STEP Model

C28992052

SemiconductorWLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3 · 27 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3)A2PB6A4PB7A6PF3-BOOT0A8VSSB1PA14B3PB5B5PA12[PA10]B7VDDB9PC14-OSC32_IC2PA13C4PA11[PA9]C6PA0-CK_INC8PC15-OSC32_OD1PA10F9VDDA/VREF+F7PA3F5PA4F3PB0F1PB1E8PA2E6PA5E4PA7E2PA8D9PF2-NRSTD7PA1D5PA6D3PA9Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
B1D1F1A2C2E2B3D3F3A4C4E4B5D5F5A6C6E6B7D7F7A8C8E8B9D9F9E=2.60mm · Pitch e=0.40mmD=2.30mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.60mm × 2.30mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (27/27)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A2PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
A4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
A6PF3-BOOT0I/OMultiplexed I/O & Peripheral Pin PF3-BOOT0 (General)
A8VSSGNDGround Reference Pin (VSS)
B1PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
B3PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
B5PA12[PA10]I/OMultiplexed I/O & Peripheral Pin PA12[PA10] (General)
B7VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
B9PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
C2PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
C4PA11[PA9]I/OMultiplexed I/O & Peripheral Pin PA11[PA9] (General)
C6PA0-CK_INI/OMultiplexed I/O & Peripheral Pin PA0-CK_IN (General)
C8PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
D1PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
D3PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
D5PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
D7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
D9PF2-NRSTI/OMultiplexed I/O & Peripheral Pin PF2-NRST (General)
E2PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
E4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
E6PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
E8PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
F1PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
F3PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
F5PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
F7PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
F9VDDA/VREF+PowerPower Supply Input (VDDA/VREF+ — 3.3V / 5.0V Standard Logic)
PIN A2 PB6
I/O
Multiplexed I/O & Peripheral Pin PB6 (General)
Design note: Signal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C28992052 (Semiconductor · WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3) - 2. Standard Pinout (Top View)
True package pinout (27 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3) - 4. Package Dimensions (D×E×A)
WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3 · 2.60×2.30mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3) - 5. Recommended Land Pattern
IPC-7351B Footprint (27 Pads)Expand ›
6. Application SchematicSCHEMATIC
C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C28992052)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3) is a 27-pin standard electronic & interconnect component featuring a 2.30 × 2.60 × 0.55 mm mechanical envelope (lead pitch e = 0.39 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.30 × 2.60 × 0.55 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3)
Pin Count & Lead PitchN / e
27 Pins | Pitch e = 0.39 mm (15.4 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol27 auto-grouped pins
OK
IPC-7351B Land Pattern27 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32U031 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.30 × 2.60 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
27P / 27Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3)?

Manufactured by Semiconductor, the C28992052 is housed in a WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3 package with 27 pins and a 0.40 mm lead pitch. Key pins include: A2 (PB6: Multiplexed I/O & Peripheral Pin PB6 (General)), A4 (PB7: Multiplexed I/O & Peripheral Pin PB7 (General)), A6 (PF3-BOOT0: Multiplexed I/O & Peripheral Pin PF3-BOOT0 (General)), A8 (VSS: Ground Reference Pin (VSS)), B1 (PA14: Multiplexed I/O & Peripheral Pin PA14 (General)), B3 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)).

What are the IPC-7351B PCB Footprint dimensions for C28992052?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C28992052 (WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3) has a nominal body envelope of 2.60 × 2.30 mm, pitch e = 0.40 mm, and 27 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C28992052?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C28992052 (Semiconductor, WLCSP-27_L2.6-W2.3-P0.20-TL_STM32U031G8Y3) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (27 pins) & STM32U031 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A2PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
A4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
A6PF3-BOOT0Digital_IOSignal terminal PF3-BOOT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF3-BOOT0. Supported peripheral buses: General.
A8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B1PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
B3PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
B5PA12[PA10]Digital_IOSignal terminal PA12[PA10] (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12[PA10]. Supported peripheral buses: General.
B7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B9PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
C2PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
C4PA11[PA9]Digital_IOSignal terminal PA11[PA9] (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11[PA9]. Supported peripheral buses: General.
C6PA0-CK_INDigital_IOSignal terminal PA0-CK_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0-CK_IN. Supported peripheral buses: General.
C8PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
D1PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
D3PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
D5PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
D7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
D9PF2-NRSTDigital_IOSignal terminal PF2-NRST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF2-NRST. Supported peripheral buses: General.
E2PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
E4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
E6PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
E8PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
F1PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
F3PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
F5PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
F7PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
F9VDDA/VREF+Power_InPrimary positive power supply input (VDDA/VREF+) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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